Features
•
One of a Family of Devices with User Memories from 1 Kbit to 1 Mbit
•
2-Kbit EEPROM User Memory
– Four 64 x 8 (512-bit) Zones
– Self-timed Write Cycle (5 ms)
– Single Byte or 16-byte Page Write Mode
– Programmable Access Rights for Each Zone
2-Kbit Configuration Zone
– 37-byte OTP Area for User-defined Codes
– 160-byte Area for User-defined Keys and Passwords
Low Voltage Operation: 2.7V to 5.5V
Dual Protocol
– ISO 7816-3 Asynchronous T = 0 Protocol
– Synchronous Two-wire Protocol
High Security Features
– 64-bit Patented Dynamic Symetric Mutual Authentication Protocol (Under
Exclusive Patent License from
ELVA)
– Encrypted Checksum
– Stream Encryption
– Four Key Sets for Authentication and Encryption
– Eight Sets of Two 24-bit Passwords
– Anti-tearing Function
– Voltage and Frequency Monitor
High Reliability
– Endurance: 100,000 Cycles
– Data Retention: 10 years
– ESD Protection: 4,000V min
ISO-compliant Bond Pad Locations and Package Options
•
•
•
•
8 x 64 x 4
CryptoMemory
™
AT88SC0204C
Summary
•
•
Table 1.
Pin Configuration
Pad
VCC
GND
SCL/CLK
SDA/IO
RST
Description
Supply Voltage
Ground
Serial Clock Input
Serial Data Input/Output
Reset Input
ISO Module Contact
C1
C5
C3
C7
C2
Standard Package Pin
8
4
6
5
NC
Card Module Contact
VCC = C1
RST = C2
SCL/CLK = C3
NC = C4
C5 = GND
C6 = NC
C7 = SDA/IO
C8 = NC
8-lead SOIC, PDIP or LAP
NC
NC
NC
GND
1
2
3
4
8
7
6
5
VCC
NC
SCL
SDA
Rev. 2022BS–SMEM–10/02
Note: This is a summary document. A complete document is
available under NDA. For more information, please contact your
local Atmel sales office.
1
Description
The AT88SC0204C member of the CryptoMemory family is a high-performance secure
memory providing 2 Kbits of user memory with advanced security and cryptographic
features built in. The user memory is divided into 4 zones, each of which may be individ-
ually set with different security access rights or combined together to provide space for 1
to 4 data files. The AT88SC0204C provides high security, low cost and ease of imple-
mentation for smart card applications without the need for a microprocessor operating
system. The embedded cryptographic engine provides for a dynamic, symmetric-mutual
authentication between the device and host, as well as performing stream encryption for
all data and passwords exchanged between the device and host. Up to four unique key
sets may be used for these operations. The AT88SC0204C offers the ability to commu-
nicate with virtually any smart card reader using the asynchronous T = 0 protocol
defined in ISO 7816-3. For closed systems or applications using the device on a circuit
board, the AT88SC0204C will also communicate using a synchronous two-wire protocol
at clock speeds up to 1.5 MHz. In this communication mode, up to 15 devices may be
connected and individually addressed on the same serial data bus. The two-wire proto-
col may also be used for high-speed personalization of the device in card form.
Figure 1.
Block Diagram
VCC
GND
Power
Management
Authentication,
Encryption and
Certification Unit
Random
Generator
Synchronous
Interface
SCL/CLK
SDA/IO
RST
Asynchronous
ISO Interface
Reset Block
Data Transfer
Password
Verification
Answer to Reset
EEPROM
Pin Descriptions
Supply Voltage (V
CC
)
Clock (SCL/CLK)
The V
CC
input is a 2.7V to 5.5V positive voltage supplied by the host.
In the asynchronous T = 0 protocol, the SCL/CLK input is used to provide the device
with a carrier frequency
f.
The nominal length of one bit emitted on I/O is defined as an
“elementary time unit” (ETU) and is equal to 372/f.
When the synchronous protocol is used, the SCL/CLK input is used to positive edge
clock data into the device and negative edge clock data out of the device.
Serial Data (SDA/IO)
The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and
may be wired with any number of other open drain or open collector devices. An exter-
nal pull-up resistor should be connected between SDA and V
CC
. The value of this
resistor and the system capacitance loading the SDA bus will determine the rise time of
SDA. This rise time will determine the maximum frequency during read operations. Low
value pull-up resistors will allow higher frequency operations while drawing higher aver-
age power supply current.
The AT88SC0204C provides an ISO 7816-3 compliant asynchronous answer to reset
sequence. When the reset sequence is activated, the device will output the data pro-
Reset (RST)
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AT88SC0204C
2022BS–SMEM–10/02
AT88SC0204C
grammed into the 64-bit answer-to-reset register. An internal pull-up on the RST input
pad allows the device to be used in synchronous mode without bonding RST. The
AT88SC0204C does not support the synchronous answer-to-reset sequence.
Device Architecture
User Zones
The EEPROM user memory is divided into 4 zones of 512 bits each. Multiple zones
allow for different types of data or files to be stored in different zones. Access to the user
zones is allowed only after security requirements have been met. These security
requirements are defined by the user during the personalization of the device in the con-
figuration zone. If the same security requirements are selected for multiple zones, then
these zones may effectively be accessed as one larger zone.
Table 2.
User Zones
ZONE
$0
$1
$2
$3
$4
$5
$6
$7
$000
64 bytes
User 0
–
$038
$000
64 bytes
User 1
–
$038
$000
64 bytes
User 2
–
$038
$000
64 bytes
User 3
–
$038
–
–
–
–
Control Logic
Access to the user zones occurs only through the control logic built into the device. This
logic is configurable through access registers, key registers and keys programmed into
the configuration zone during device personalization. Also implemented in the control
logic is a cryptographic engine for performing the various higher-level security functions
of the device.
3
2022BS–SMEM–10/02
Configuration Zone
The configuration zone consists of 2048 bits of EEPROM memory used for storing pass-
words, keys and codes and defining security levels to be used for each user zone.
Access rights to the configuration zone are defined in the control logic and may not be
altered by the user.
Table 3.
Configuration Zone
Component
Answer to Reset
Fab Code
Memory Test Zone
Card Manufacturers Code
Lot History Code
Device Configuration Register
Identification Number
Access Registers
Password/Key Registers
Issuer Code
Authentication Attempts Counters
Cryptograms
Session Encryption Keys
Secret Seeds
Password Attempts Counters
Write Passwords
Read Passwords
Reserved
$B0
$50
$18
Address
$00
Security Fuses
There are three fuses on the device that must be blown during the device personaliza-
tion process. Each fuse locks certain portions of the configuration zone as OTP
memory. Fuses are designed for the module manufacturer, card manufacturer and card
issuer and should be blown in sequence, although all programming of the device and
blowing of the fuses may be performed at one final step.
4
AT88SC0204C
2022BS–SMEM–10/02
AT88SC0204C
Protocol Selection
The AT88SC0204C is compatible with two different communication protocols: asynchro-
nous T = 0 as defined by ISO 7816-3 or synchronous two-wire protocol. The power-up
sequence determines which of the two protocols will be used.
The power-up sequence complies with ISO 7816-3 for a cold reset.
•
•
•
•
V
CC
goes high; RST, I/O-SDA and CLK-SCL are low.
Set I/O-SDA in receive mode.
Provide a clock signal to CLK-SCL.
RST goes high after 400 clock cycles.
Asynchronous
T = 0 Protocol
The device will respond with a 64-bit ATR code, including historical bytes to indicate the
memory density within the CryptoMemory family. Once the asynchronous mode has
been selected, it is not possible to switch to the synchronous mode without powering off
the device.
Figure 2.
Asynchronous T = 0 Protocol
Vcc
I/O-SDA
RST
CLK-SCL
ATR
Synchronous
Two-wire Protocol
The synchronous mode is the default after powering up V
CC
due to the internal pull-up
on RST.
•
•
Power-up V
CC
, RST goes high also.
After stable V
CC
, CLK-SCL and I/O-SDA may be driven.
Figure 3.
Synchronous Two-wire Protocol
Vcc
I/O-SDA
RST
CLK-SCL
Note:
1
2
3
4
Four clock pulses must be sent before the first command is issued.
5
2022BS–SMEM–10/02
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