64MB, 128MB, 256MB (x64, SR)
172-PIN DDR SDRAM MICRODIMM
DDR SDRAM
MICRODIMM
Features
• 172-pin, Micro dual in-line memory module
• Utilizes 266 MT/s and 333 MT/s DDR SDRAM
components
• Fast data transfer rates: PC2100 or PC2700
• 64MB (8 Meg x 64), 128MB (16 Meg x 64), and
256MB (32 Meg x 64)
• V
DD
= V
DD
Q= +2.5V
• V
DDSPD
= +2.3V to +3.6V
• 2.5V I/O (SSTL_2 compatible)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
• Internal, pipelined double data rate (DDR)
architecture; two data accesses per clock cycle
• Bidirectional data strobe (DQS) transmitted/
received with data—i.e., source-synchronous data
capture
• Differential clock inputs (CK and CK#)
• Four internal device banks for concurrent operation
• Selectable burst lengths: 2, 4, or 8
• Auto precharge option
• Auto Refresh and Self Refresh Modes: 15.625µs
(64MB) or 7.8125µs (128MB, 256MB) maximum
average periodic refresh interval
• Serial Presence Detect (SPD) with EEPROM
• Selectable READ CAS latency for maximum
compatibility
• Gold edge contacts
For the latest data sheet, please refer to the Micron
Web
site:
www.micron.com/products/modules
MT4VDDT864W – 64MB
MT4VDDT1664W – 128MB
MT4VDDT3264W – 256MB
Figure 1: 172-pin MicroDIMM (MO-214)
1.181in. (30.00mm)
OPTIONS
MARKING
• Package
172-pin MicroDIMM (standard)
172-pin MicroDIMM (lead-free)
• Memory Clock, Speed, CAS Latency
2
6ns (167 MHz), 333 MT/s, CL = 2.5
7.5ns (133 MHz), 266 MT/s, CL = 2
7.5ns (133 MHz), 266 MT/s, CL = 2
7.5ns (133 MHz), 266 MT/s, CL = 2.5
• PCB
1.181in. (30.00mm)
NOTE:
G
Y
1
-335
-262
1
-26A
1
-265
1. Contact Micron for product availability.
2. CL = CAS (READ) latency.
Table 1:
Address Table
64MB
128MB
8K
8K(A0–A12)
4 (BA0, BA1)
256Mb (16 Meg x 16)
512 (A0–A8)
1 (S0#)
256MB
8K
8K(A0–A12)
4 (BA0, BA1)
512Mb (32 Meg x 16)
1K (A0–A9)
1 (S0#)
4K
4K (A0–A11)
4 (BA0, BA1)
128Mb (8 Meg x 16)
512 (A0–A8)
1 (S0#)
Refresh Count
Row Addressing
Device Bank Addressing
Device Configuration
Column Addressing
Module Rank Addressing
pdf: 09005aef80d71611, source: 09005aef80d7157a
DD4C8_16x64WG.fm - Rev. D 9/04 EN
1
©2004 Micron Technology, Inc.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
64MB, 128MB, 256MB (x64, SR)
172-PIN DDR SDRAM MICRODIMM
Table 2:
Part Numbers and Timing Parameters
MODULE
MODULE
DENSITY CONFIGURATION BANDWIDTH
64MB
64MB
64MB
64MB
64MB
64MB
64MB
64MB
128MB
128MB
128MB
128MB
128MB
128MB
128MB
128MB
256MB
256MB
256MB
256MB
256MB
256MB
256MB
256MB
8 Meg x 64
8 Meg x 64
8 Meg x 64
8 Meg x 64
8 Meg x 64
8 Meg x 64
8 Meg x 64
8 Meg x 64
16 Meg x 64
16 Meg x 64
16 Meg x 64
16 Meg x 64
16 Meg x 64
16 Meg x 64
16 Meg x 64
16 Meg x 64
32 Meg x 64
32 Meg x 64
32 Meg x 64
32 Meg x 64
32 Meg x 64
32 Meg x 64
32 Meg x 64
32 Meg x 64
2.7 GB/s
2.7 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.7 GB/s
2.7 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.7 GB/s
2.7 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
MEMORY CLOCK
DATA RATE
6ns, 333 MT/s
6ns, 333 MT/s
7.5ns, 266 MT/s
7.5ns ,266 MT/s
7.5ns, 266 MT/s
7.5ns, 266 MT/s
7.5ns, 266 MT/s
7.5ns, 266 MT/s
6ns, 333 MT/s
6ns, 333 MT/s
7.5ns, 266 MT/s
7.5ns ,266 MT/s
7.5ns, 266 MT/s
7.5ns, 266 MT/s
7.5ns, 266 MT/s
7.5ns, 266 MT/s
6ns, 333 MT/s
6ns, 333 MT/s
7.5ns, 266 MT/s
7.5ns ,266 MT/s
7.5ns, 266 MT/s
7.5ns, 266 MT/s
7.5ns, 266 MT/s
7.5ns, 266 MT/s
CLOCK LATENCY
(CL -
t
RCD -
t
RP)
2.5-3-3
2.5-3-3
2-2-2
2-2-2
2-3-3
2-3-3
2.5-3-3
2.5-3-3
2.5-3-3
2.5-3-3
2-2-2
2-2-2
2-3-3
2-3-3
2.5-3-3
2.5-3-3
2.5-3-3
2.5-3-3
2-2-2
2-2-2
2-3-3
2-3-3
2.5-3-3
2.5-3-3
PART NUMBER
MT4VDDT864WG-335__
MT4VDDT864WY-335__
MT4VDDT864WG-262__
MT4VDDT864WY-262__
MT4VDDT864WG-26A__
MT4VDDT864WY-26A__
MT4VDDT864WG-265__
MT4VDDT864WY-265__
MT4VDDT1664WG-335__
MT4VDDT1664WY-335__
MT4VDDT1664WG-262__
MT4VDDT1664WY-262__
MT4VDDT1664WG-26A__
MT4VDDT1664WY-26A__
MT4VDDT1664WG-265__
MT4VDDT1664WY-265__
MT4VDDT3264WG-335__
MT4VDDT3264WY-335__
MT4VDDT3264WG-262__
MT4VDDT3264WY-262__
MT4VDDT3264WG-26A__
MT4VDDT3264WY-26A__
MT4VDDT3264WG-265__
MT4VDDT3264WY-265__
NOTE:
All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for
current revision codes. Example: MT4VDDT1664WG-265A1.
pdf: 09005aef80d71611, source: 09005aef80d7157a
DD4C8_16x64WG.fm - Rev. D 9/04 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
64MB, 128MB, 256MB (x64, SR)
172-PIN DDR SDRAM MICRODIMM
Table 3:
Pin Assignment
(172-Pin MicroDIMM Front)
45
V
DD
47
DQS2
49
DQ18
51
V
SS
53
DQ19
55
DQ24
57
V
DD
59
DQ25
61
DQS3
63
V
SS
65
DQ26
67
DQ27
69
V
DD
71
DNU
73
NC/A12
1
75
A9
77
A7
79
V
SS
81
A5
83
A3
85
A1
87 A10/AP
131
89
V
DD
133
91
BA0
135
93
WE#
137
95
S0#
139
97
NC
141
99
V
SS
143
101 DQ32 145
103 DQ33
147
105
V
DD
149
107 DQS4
151
109 DQ34
153
111
V
SS
155
113 DQ35
157
115 DQ40
159
117
119
121
123
125
127
129
V
DD
DQ41
DQS5
V
SS
DQ42
DQ43
V
DD
V
DD
V
SS
V
SS
DQ48
DQ49
V
DD
DQS6
DQ50
V
SS
DQ51
DQ56
V
DD
DQ57
DQS7
V
SS
Table 4:
Pin Assignment
(172-pin MicroDIMM Back)
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
V
DD
DM2
DQ22
V
SS
DQ23
DQ28
V
DD
DQ29
DM3
V
SS
DQ30
DQ31
V
DD
CKE0
A11
A8
A6
V
SS
A4
A2
A0
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
BA1
V
DD
RAS#
CAS#
DNU
NC
V
SS
DQ36
DQ37
V
DD
DM4
DQ38
V
SS
DQ39
DQ44
V
DD
DQ45
DM5
V
SS
DQ46
DQ47
V
DD
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
CK1#
CK1
V
SS
DQ52
DQ53
V
DD
DM6
DQ54
V
SS
DQ55
DQ60
V
DD
DQ61
DM7
V
SS
DQ62
DQ63
V
DD
SA0
SA1
SA2
PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
NOTE:
PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
V
REF
V
SS
DQ4
DQ5
V
DD
DM0
DQ6
V
SS
DQ7
DQ12
V
DD
DQ13
DM1
V
SS
DQ14
DQ15
V
DD
V
DD
V
SS
V
SS
DQ20
DQ21
V
REF
V
SS
DQ0
DQ1
V
DD
DQS0
DQ2
V
SS
DQ3
DQ8
V
DD
DQ9
DQS1
V
SS
DQ10
DQ11
V
DD
CK0
CK0#
V
SS
DQ16
DQ17
161 DQ58
163 DQ59
165
V
DD
167
SDA
169
SCL
171 V
DDSPD
1.
Pin 73 is NC for the 64MB module. It is A12 for the 128MB and 256MB modules.
Figure 2: 172-Pin MicroDIMM Pinout
Front View
Back View
U5
U1
U2
U4
U3
PIN 1
(All Odd Numbered Pins)
PIN 171
PIN 172
(All Even Numbered Pins)
Indicates a V
SS
pin
PIN 2
Indicates a V
DD
or V
DDQ
pin
pdf: 09005aef80d71611, source: 09005aef80d7157a
DD4C8_16x64WG.fm - Rev. D 9/04 EN
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
64MB, 128MB, 256MB (x64, SR)
172-PIN DDR SDRAM MICRODIMM
Table 5:
Pin Descriptions
SYMBOL
WE#, CAS#,
RAS#
CK0, CK0#
CK1, CK1#
TYPE
Input
Input
DESCRIPTION
Command Inputs: RAS#, CAS#, and WE# (along with S#)
define the command being entered.
Clock: CK and CK# are differential clock inputs. All address
and control input signals are sampled on the crossing of the
positive edge of CK and negative edge of CK#. Output data
(DQs and DQS) is refer- enced to the crossings of CK and CK#.
Clock Enable: CKE HIGH activates and CKE LOW deactivates
the internal clock, input buffers, and output drivers. Taking
CKE LOW provides PRECHARGE POWER-DOWN and SELF
REFRESH operations (all device banks idle), or ACTIVE
POWER-DOWN (row ACTIVE in any device bank). CKE is
synchronous for POWER-DOWN entry and exit, and for SELF
REFRESH entry. CKE is asynchronous for SELF REFRESH exit
and for disabling the outputs. CKE must be maintained HIGH
throughout read and write accesses. Input buffers (excluding
CK, CK# and CKE) are disabled during POWER-DOWN. Input
buffers (excluding CKE) are disabled during SELF REFRESH.
CKE is an SSTL_2 input but will detect an LVCMOS LOW level
after V
DD
is applied and until CKE is first brought HIGH. After
CKE is brought HIGH, it becomes an SSTL_2 input only.
Chip Select: S# enables (registered LOW) and disables
(registered HIGH) the command decoder. All commands are
masked when S# is registered HIGH. S# is considered part of
the command code.
Bank Address: BA0 and BA1 define to which device bank an
ACTIVE, READ, WRITE, or PRECHARGE command is being
applied.
Address Inputs: Provide the row address for ACTIVE
commands, and the column address and auto precharge bit
(A10) for READ/WRITE commands, to select one location out
of the memory array in the respective device bank. A10
sampled during a PRECHARGE command determines
whether the PRECHARGE applies to one device bank (A10
LOW, device bank selected by BA0, BA1) or all device banks
(A10 HIGH). The address inputs also provide the op-code
during a MODE REGISTER SET command. BA0 and BA1 define
which mode register (mode register or extended mode
register) is loaded during the LOAD MODE REGISTER
command.
Data Mask: DM is an input mask signal for write data. Input
data is masked when DM is sampled HIGH along with that
input data during a WRITE access. DM is sampled on both
edges of DQS. Although DM pins are input-only, the DM
loading is designed to match that of DQ and DQS pins.
Data Strobe: Output with READ data, input with WRITE data.
DQS is edge-aligned with READ data, centered in WRITE
data. Used to capture data.
Pin numbers may not correlate with symbols; refer to Pin Assignment tables on page 3 for more information
PIN NUMBERS
92, 93, 94
35, 37, 132, 134
72
CKE0
Input
95
S0#
Input
88, 91
BA0, BA1
Input
73
(128MB, 256MB),
75, 77,
81, 83, 85, 87, 74, 76, 78, 82,
84, 86
A0–A11
(64MB)
A0–A12
(128MB, 256MB)
Input
12, 26, 48, 62, 108, 122, 144,
158
DM0–DM7
Input
11, 25, 47, 61, 107, 121, 143,
157
DQS0–DQS7
Input/
Output
pdf: 09005aef80d71611, source: 09005aef80d7157a
DD4C8_16x64WG.fm - Rev. D 9/04 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
64MB, 128MB, 256MB (x64, SR)
172-PIN DDR SDRAM MICRODIMM
Table 5:
Pin Descriptions
SYMBOL
DQ0–DQ63
TYPE
Input/
Output
Data I/Os: Data bus.
DESCRIPTION
Pin numbers may not correlate with symbols; refer to Pin Assignment tables on page 3 for more information
PIN NUMBERS
5, 7, 13, 17, 19, 23, 29, 31 41,
43, 49, 53, 55, 59, 65, 67, 101,
103, 109, 113, 115, 119, 125,
127, 137, 139, 145, 149, 151,
155, 161, 163, 6, 8, 14, 18, 20,
24, 30, 32, 42, 44, 50, 54, 56,
60, 66, 68, 102, 104, 110, 114,
116, 120, 126, 128, 138, 140,
146, 150, 152, 156, 162, 164
167
SDA
Input/
Output
Input
Input
Supply
Supply
169
168, 170, 172
1, 2
9, 21, 33, 45, 57, 69, 89, 105,
117, 129, 131, 141, 153, 165,
10, 22, 34, 36, 46, 58, 90, 106,
118, 130 142, 154, 166
3, 15, 27, 39, 51, 63, 99, 111,
123, 133, 135, 147, 159, 4, 16,
28, 38,40, 52, 64, 100, 112,
124, 136, 148, 160
171
73 (64MB), 97, 98
71, 96
SCL
SA0–SA2
V
REF
V
DD
Serial Presence-Detect Data: SDA is a bidirectional pin used
to transfer addresses and data into and out of the presence-
detect portion of the module.
Serial Clock for Presence-Detect: SCL is used to synchronize
the presence-detect data transfer to and from the module.
Presence-Detect Address Inputs: These pins are used to
configure the presence-detect device.
SSTL_2 reference voltage.
DQ Power Supply: +2.5V ±0.2V.
V
SS
Supply
Ground: +2.3V to +3.6V.
V
DDSPD
NC
DNU
Supply
–
–
Serial EEPROM positive power supply.
No Connect: These pins should be left unconnected.
Do Not Use: These pins are not connected on this module but
are assigned pins on other modules in this product family.
pdf: 09005aef80d71611, source: 09005aef80d7157a
DD4C8_16x64WG.fm - Rev. D 9/04 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
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