QL4016 QuickRAM Data Sheet
• • • • • •
16,000 Usable PLD Gate QuickRAM ESP Combining Performance,
Density and Embedded RAM
Device Highlights
High Performance & High Density
•
16,000 Usable PLD Gates with 118 I/Os
•
300 MHz 16-bit Counters, 400 MHz
Advanced I/O Capabilities
•
Interfaces with both 3.3 V and 5.0 V devices
•
PCI compliant with 3.3 V and 5.0 V busses
Datapaths, 160+ MHz FIFOs
•
0.35
µm
four-layer metal non-volatile
CMOS process for smallest die sizes
for -1/-2/-3/-4 speed grades
•
Full JTAG boundary scan
•
I/O Cells with individually controlled
Registered Input Path and Output Enables
High Speed Embedded SRAM
•
10 dual-port RAM modules, organized in
user-configurable 1,152 bit blocks
•
5 ns access times, each port independently
accessible
•
Fast and efficient for FIFO, RAM, and ROM
functions
10
RAM
Blocks
320
High Speed
Logic Cells
Easy to Use / Fast Development
Cycles
•
100% routable with 100% utilization and
Interface
complete pin-out stability
•
Variable-grain logic cells provide high
performance and 100% utilization
•
Comprehensive design tools include high
quality Verilog/VHDL synthesis
Figure 1: QuickRAM Block Diagram
© 2002 QuickLogic Corporation
www.quicklogic.com
•
•
•
•
•
•
1
QL4016 QuickRAM Data Sheet Rev I
Architecture Overview
The QuickRAM family of ESPs (Embedded Standard Products) offers FPGA logic in
combination with Dual-Port SRAM modules. The QL4016 is a 16,000 usable PLD gate
member of the QuickRAM family of ESPs. QuickRAM ESPs are fabricated on a 0.35
µm
four-layer metal process using QuickLogic's patented ViaLink
TM
technology to provide a
unique combination of high performance, high density, low cost, and extreme ease-of-use.
The QL4016 contains 320 logic cells and 10 Dual Port RAM modules (see
Figure 1
). Each
RAM module has 1,152 RAM bits, for a total of 11,520 bits. RAM Modules are Dual Port
(one read port, one write port) and can be configured into one of four modes:
64 (deep)
×
18 (wide), 128
×
9, 256
×
4, or 512
×
2 (see
Figure 4
). With a maximum of 82
I/Os, the QL4016 is available in 84-pin PLCC, 100-pin TQFP, 100-pin CQFP and 144-pin
TQFP packages.
Designers can cascade multiple RAM modules to increase the depth or width allowed in
single modules by connecting corresponding address lines together and dividing the words
between modules (see
Figure 2
). This approach allows up to 512-deep configurations as
large as 16 bits wide in the smallest QuickRAM device and 44 bits wide in the largest device.
Software support for the complete QuickRAM family, including the QL4016, is available
through two basic packages. The turnkey QuickWorks
TM
package provides the most
complete ESP software solution from design entry to logic synthesis, to place and route, to
simulation. The QuickTools package provides a solution for designers who use Cadence,
Exemplar, Mentor, Synopsys, Synplicity, Viewlogic, Aldec, or other third-party tools for
design entry, synthesis, or simulation.
The QuickLogic
TM
variable grain logic cell features up to 16 simultaneous inputs and five
outputs within a cell that can be fragmented into five independent cells. Each cell has a fan-
in of 29 including register and control lines (see
Figure 3
).
WDATA
RAM
Module
(1,152 bits)
RDATA
WADDR
RADDR
RAM
Module
(1,152 bits)
WDATA
RDATA
Figure 2: QuickRAM Module Bits
2
•
•
•
www.quicklogic.com
•
•
•
© 2002 QuickLogic Corporation
QL4016 QuickRAM Data Sheet Rev I
Product Summary
Total of 118 I/O Pins
•
110 bi-directional input/output pins, PCI-compliant for 5.0 V and 3.3 V buses for
-1/-2/-3/-4 speed grades
•
8 high-drive input/distributed network pins
Eight Low-Skew Distributed Networks
•
Two array clock/control networks available to the logic cell flip-flop clock, set and reset
inputs—each driven by an input-only pin
•
Six global clock/control networks available to the logic cell F1, clock, set and reset inputs
and the input and I/O register clock, reset and enable inputs as well as the output enable
contro—each driven by an input-only or I/O pin, or any logic cell output or I/O cell
feedback
High Performance Silicon
•
Input + logic cell + output total delays = under 6 ns
•
Data path speeds over 400 MHz
•
Counter speeds over 300 MHz
•
FIFO speeds over 160+ MHz
© 2002 QuickLogic Corporation
•
www.quicklogic.com
•
•
•
•
•
3
QL4016 QuickRAM Data Sheet Rev I
Electrical Specifications
AC Characteristics at V
CC
= 3.3 V, TA = 25°C (K = 1.00)
To calculate delays, multiply the appropriate K factor from
Table 10: Operating Range
by the
following numbers in the tables provided.
QS
A1
A2
A3
A4
A5
A6
QS
OP
B1
B2
C1
C2
MP
MS
D1
D2
E1
E2
NP
NS
F1
F2
F3
F4
F5
F6
QC
QR
AZ
OZ
QZ
NZ
FZ
Figure 3: QuickRAM Logic Cell
Table 1: Logic Cell
Symbol
Parameter
1
t
PD
t
SU
t
H
t
CLK
t
CWHI
t
CWLO
t
SET
t
RESET
t
SW
t
RW
Combinatorial Delay
a
Setup Time
a
Hold Time
Clock to Q Delay
Clock High Time
Clock Low Time
Set Delay
Reset Delay
Set Width
Reset Width
1.4
1.7
0.0
0.7
1.2
1.2
1.0
0.8
1.9
1.8
Propagation Delays (ns)
Fanout (5)
2
1.7
1.7
0.0
1.0
1.2
1.2
1.3
1.1
1.9
1.8
3
1.9
1.7
0.0
1.2
1.2
1.2
1.5
1.3
1.9
1.8
4
2.2
1.7
0.0
1.5
1.2
1.2
1.8
1.6
1.9
1.8
5
3.2
1.7
0.0
2.5
1.2
1.2
2.8
2.6
1.9
1.8
a. These limits are derived from a representative selection of the slowest paths through the Quick-
RAM logic cell including typical net delays. Worst case delay values for specific paths should be
determined from timing analysis of your particular design.
4
•
•
•
www.quicklogic.com
•
•
•
© 2002 QuickLogic Corporation
QL4016 QuickRAM Data Sheet Rev I
[8:0]
[17:0]
WA
WD
WE
WCLK
RE
RCLK
RA
RD
ASYNCRD
[8:0]
[17:0]
[1:0]
MODE
Figure 4: QuickRAM Module
Table 2: RAM Cell Synchronous Write Timing
Symbol
Parameter
1
t
SWA
t
HWA
t
SWD
t
HWD
t
SWE
t
HWE
t
WCRD
WA Setup Time to WCLK
WA Hold Time to WCLK
WD Setup Time to WCLK
WD Hold Time to WCLK
WE Setup Time to WCLK
WE Hold Time to WCLK
WCLK to RD (WA=RA)
a
1.0
0.0
1.0
0.0
1.0
0.0
5.0
Propagation Delays (ns)
Fanout
2
1.0
0.0
1.0
0.0
1.0
0.0
5.3
3
1.0
0.0
1.0
0.0
1.0
0.0
5.6
4
1.0
0.0
1.0
0.0
1.0
0.0
5.9
5
1.0
0.0
1.0
0.0
1.0
0.0
7.1
a. Stated timing for worst case Propagation Delay over process variation at V
CC
= 3.3 V and
TA = 25
°
C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature
settings as specified in the Operating Range.
Table 3: RAM Cell Synchronous Read Timing
Symbol
Logic Cells
t
SRA
t
HRA
t
SRE
t
HRE
t
RCRD
RA Setup Time to RCLK
RA Hold Time to RCLK
RE Setup Time to RCLK
RE Hold Time to RCLK
RCLK to RD
a
Parameter
1
1.0
0.0
1.0
0.0
4.0
Propagation Delays (ns)
Fanout
2
1.0
0.0
1.0
0.0
4.3
3
1.0
0.0
1.0
0.0
4.6
4
1.0
0.0
1.0
0.0
4.9
5
1.0
0.0
1.0
0.0
6.1
a. Stated timing for worst case Propagation Delay over process variation at V
CC
= 3.3 V and
TA = 25
×
C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature
settings as specified in the Operating Range.
•
www.quicklogic.com
•
•
•
•
•
© 2002 QuickLogic Corporation
5
京公网安备 11010802033920号
EEWORLD
