A32200DX-1PQG208I datasheet, PDF

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A32200DX-1PQG208I: DescriptionField Programmable Gate Array, 2414-Cell, CMOS, PQFP208,; CategoryProgrammable logic devices Programmable logic; File Size2MB，84 Pages; ManufacturerMicrosemi; Websitehttps://www.microsemi.com; Environmental Compliance

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A32200DX-1PQG208I Overview

Field Programmable Gate Array, 2414-Cell, CMOS, PQFP208,

A32200DX-1PQG208I Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Objectid	112999718
package instruction	QFP, QFP208,1.2SQ,20
Reach Compliance Code	compliant
JESD-30 code	S-PQFP-G208
Humidity sensitivity level	3
Number of entries	176
Number of logical units	2414
Output times	176
Number of terminals	208
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	QFP
Encapsulate equivalent code	QFP208,1.2SQ,20
Package shape	SQUARE
Package form	FLATPACK
Peak Reflow Temperature (Celsius)	245
power supply	5 V
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30

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v3.0

Integrator Series FPGAs:

1200XL and 3200DX Families

Fe a t ur es

High C apaci t y

G en er al D e sc r i p t i on

•

2,500 to 30,000 Logic Gates

Up to 3Kbits Configurable Dual-Port SRAM

Fast Wide-Decode Circuitry

Up to 250 User-Programmable I/O Pins

225 MHz Performance

5 ns Dual-Port SRAM Access

100 MHz FIFOs

7.5 ns 35-Bit Address Decode

High P er f or m ance

Actel’s Integrator Series FPGAs are the first programmable

logic devices optimized for high-speed system logic

integration. Based on Actel’s proprietary antifuse

technology and 0.6-micron double metal CMOS process,

Integrator Series devices offer a fine-grained, register-rich

architecture with embedded dual-port SRAM and

wide-decode circuitry.

Integrator Series’ 3200DX and 1200XL families were

designed to integrate system logic which is typically

implemented in multiple CPLDs, PALs, and FPGAs. These

devices provide the features and performance required for

today’s complex, high-speed digital logic systems. The

3200DX family offers fast dual-port SRAM for implementing

FIFOs, LIFOs, and temporary data storage. The large

number of storage elements can efficiently address

applications requiring wide datapath manipulation and

transformation functions such as telecommunications,

networking, and DSP.

E ase -of- Int egr at ion

• Synthesis-Friendly Architecture Supports ASIC Design

Methodologies.

• 95–100% Device Utilization using Automatic

Place-and-Route Tools.

• Deterministic, User-Controllable Timing Via Timing

Driven Software Tools with Up To 100% Pin Fixing.

• IEEE Standard 1149.1 (JTAG) Boundary Scan Testing.

I n t eg r a t o r Se r i e s P r o du c t P r of i l e F am i l y

1200XL

Device

A1225XL

2,500

N/A

231

220

N/A

231

A1240XL

4,000

N/A

348

336

N/A

348

104

A1280XL

8,000

N/A

624

608

N/A

624

140

3200DX

A3265DX

6,500

N/A

510

475

N/A

510

126

PL84

PQ100

PQ160

TQ176

A32100DX

10,000

2,048

700

662

700

152

Yes

PL84

PQ160

PQ208

TQ176

CQ84

A32140DX

14,000

N/A

954

912

N/A

954

176

Yes

PL84

PQ160

PQ208

TQ176

CQ256

A32200DX

20,000

2,560

1,230

1,184

1,230

202

Yes

PQ208

RQ208

RQ240

CQ208

CQ256

A32300DX

30,000

3,072

1,888

1,833

1,888

250

Yes

RQ208

RQ240

CQ256

Capacity

Logic Gates

SRAM Bits

Sequential

Combinatorial

Decode

Logic Modules

SRAM Modules

(64x4 or 32x8)

Dedicated Flip-Flops

Clocks

User I/O

(Maximum)

JTAG

Packages

PL84

PQ100

VQ100

PG100

PL84 PQ100

PQ144

TQ176

PG132

PL84

PQ160 PQ208

TQ176

PG176 CQ172

Note:

Logic gate capacity does not include SRAM bits as logic.

F eb r u a r y 2 0 0 1

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