PIC32MX1XX/2XX/5XX 64/100-PIN
32-bit Microcontrollers (up to 512 KB Flash and 64 KB SRAM) with
Audio/Graphics/Touch (HMI), CAN, USB, and Advanced Analog
Operating Conditions
• 2.3V to 3.6V, -40ºC to +105ºC (DC to 40 MHz),
-40ºC to +85ºC (DC to 50 MHz)
®
Timers/Output Compare/Input Capture
• Five General Purpose Timers:
- Five 16-bit and up to two 32-bit Timers/Counters
• Five Output Compare (OC) modules
• Five Input Capture (IC) modules
• Peripheral Pin Select (PPS) to allow function remap
• Real-Time Clock and Calendar (RTCC) module
Core: 50 MHz/83 DMIPS MIPS32 M4K
®
• MIPS16e
®
mode for up to 40% smaller code size
• Code-efficient (C and Assembly) architecture
• Single-cycle (MAC) 32x16 and two-cycle 32x32 multiply
Clock Management
•
•
•
•
•
0.9% internal oscillator
Programmable PLLs and oscillator clock sources
Fail-Safe Clock Monitor (FSCM)
Independent Watchdog Timer
Fast wake-up and start-up
Communication Interfaces
• USB 2.0-compliant Full-speed OTG controller
• Up to five UART modules (12.5 Mbps):
- LIN 1.2 protocols and IrDA
®
support
• Four 4-wire SPI modules (25 Mbps)
• Two I
2
C modules (up to 1 Mbaud) with SMBus support
• PPS to allow function remap
• Parallel Master Port (PMP) with dual read/write buffers
• Controller Area Network (CAN) 2.0B Compliant with
DeviceNet™ addressing support
Power Management
• Low-power management modes (Sleep and Idle)
• Integrated Power-on Reset, Brown-out Reset, and High
Voltage Detect
• 0.5 mA/MHz dynamic current (typical)
• 44
μA
I
PD
current (typical)
Direct Memory Access (DMA)
• Four channels of hardware DMA with automatic data
size detection
• 32-bit Programmable Cyclic Redundancy Check (CRC)
• Two additional channels dedicated to USB
• Two additional channels dedicated to CAN
Audio/Graphics/Touch HMI Features
External graphics interface with up to 34 PMP pins
Audio data communication: I
2
S, LJ, RJ, USB
Audio data control interface: SPI and I
2
C
Audio data master clock:
- Generation of fractional clock frequencies
- Can be synchronized with USB clock
- Can be tuned in run-time
• Charge Time Measurement Unit (CTMU):
- Supports mTouch
®
capacitive touch sensing
- Provides high-resolution time measurement (1 ns)
•
•
•
•
Input/Output
• 10 mA or 15 mA source/sink for standard V
OH
/V
OL
and
up to 22 mA for non-standard V
OH1
• 5V-tolerant pins
• Selectable open drain, pull-ups, and pull-downs
• External interrupts on all I/O pins
Qualification and Class B Support
• AEC-Q100 REVG (Grade 2 -40ºC to +105ºC)
• Class B Safety Library, IEC 60730
Advanced Analog Features
• ADC Module:
- 10-bit 1 Msps rate with one Sample and Hold (S&H)
- Up to 48 analog inputs
- Can operate during Sleep mode
• Flexible and independent ADC trigger sources
• On-chip temperature measurement capability
• Comparators:
- Three dual-input Comparator modules
- Programmable reference with 32 voltage points
Debugger Development Support
•
•
•
•
In-circuit and in-application programming
4-wire MIPS
®
Enhanced JTAG interface
Unlimited program and six complex data breakpoints
IEEE 1149.2-compatible (JTAG) boundary scan
Packages
Type
Pin Count
I/O Pins (up to)
Contact/Lead Pitch
Dimensions
Note
1:
QFN
64
53
0.50 mm
9x9x0.9 mm
64
53
0.50 mm
10x10x1 mm
TQFP
100
85
0.40 mm
12x12x1 mm
100
85
0.50 mm
14x14x1 mm
TFBGA (see Note 1)
100
85
0.65 mm
7x7x1.2 mm
Please contact your local Microchip Sales Office for information regarding the availability of devices in the 100-pin TFBGA package.
2014-2017 Microchip Technology Inc.
DS60001290E-page 1
PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY
Device Pin Tables
TABLE 2:
PIN NAMES FOR 64-PIN GENERAL PURPOSE DEVICES
64-PIN QFN
(4)
AND TQFP (TOP VIEW)
PIC32MX120F064H
PIC32MX130F128H
PIC32MX150F256H
PIC32MX170F512H
64
1
64
QFN
(4)
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Note
AN22/RPE5/PMD5/RE5
AN23/PMD6/RE6
AN27/PMD7/RE7
AN16/C1IND/RPG6/SCK2/PMA5/RG6
AN17/C1INC/RPG7/PMA4/RG7
AN18/C2IND/RPG8/PMA3/RG8
MCLR
AN19/C2INC/RPG9/PMA2/RG9
V
SS
V
DD
AN5/C1INA/RPB5/RB5
AN4/C1INB/RB4
PGED3/AN3/C2INA/RPB3/RB3
PGEC3/AN2/CTCMP/C2INB/RPB2/CTED13/RB2
PGEC1/V
REF
-/AN1/RPB1/CTED12/RB1
PGED1/V
REF
+/AN0/RPB0/PMA6/RB0
PGEC2/AN6/RPB6/RB6
PGED2/AN7/RPB7/CTED3/RB7
AV
DD
AV
SS
AN8/RPB8/CTED10/RB8
AN9/RPB9/CTED4/PMA7/RB9
TMS/CV
REFOUT
/AN10/RPB10/CTED11/PMA13/RB10
TDO/AN11/PMA12/RB11
V
SS
V
DD
TCK/AN12/PMA11/RB12
TDI/AN13/PMA10/RB13
AN14/RPB14/SCK3/CTED5/PMA1/RB14
AN15/RPB15/OCFB/CTED6/PMA0/RB15
RPF4/SDA2/PMA9/RF4
RPF5/SCL2/PMA8/RF5
1:
2:
3:
4:
Full Pin Name
Pin #
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
RPF3/RF3
RPF2/RF2
RPF6/SCK1/INT0/RF6
SDA1/RG3
SCL1/RG2
V
DD
OSC1/CLKI/RC12
OSC2/CLKO/RC15
V
SS
RPD8/RTCC/RD8
RPD9/RD9
RPD10/PMA15/RD10
RPD11/PMA14/RD11
RPD0/RD0
SOSCI/RPC13/RC13
SOSCO/RPC14/T1CK/RC14
AN24/RPD1/RD1
AN25/RPD2/RD2
AN26/C3IND/RPD3/RD3
RPD4/PMWR/RD4
RPD5/PMRD/RD5
C3INC/RD6
C3INB/RD7
V
CAP
V
DD
C3INA/RPF0/RF0
RPF1/RF1
PMD0/RE0
PMD1/RE1
AN20/PMD2/RE2
RPE3/CTPLS/PMD3/RE3
AN21/PMD4/RE4
1
TQFP
Full Pin Name
The RPn pins can be used by remappable peripherals. See
Table 1
for the available peripherals and
Section 11.3 “Peripheral Pin
Select”
for restrictions.
Every I/O port pin (RBx-RGx) can be used as a change notification pin (CNBx-CNGx). See
Section 11.0 “I/O Ports”
for more information.
Shaded pins are 5V tolerant.
The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to V
SS
externally.
2014-2017 Microchip Technology Inc.
DS60001290E-page 3
PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY
TABLE 3:
PIN NAMES FOR 64-PIN USB DEVICES
64-PIN QFN
(4)
AND TQFP (TOP VIEW)
PIC32MX230F128H
PIC32MX530F128H
PIC32MX250F256H
PIC32MX550F256H
PIC32MX270F512H
PIC32MX570F512H
64
1
64
QFN
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Note
AN22/RPE5/PMD5/RE5
AN23/PMD6/RE6
AN27/PMD7/RE7
AN16/C1IND/RPG6/SCK2/PMA5/RG6
AN17/C1INC/RPG7/PMA4/RG7
AN18/C2IND/RPG8/PMA3/RG8
MCLR
AN19/C2INC/RPG9/PMA2/RG9
V
SS
V
DD
AN5/C1INA/RPB5/V
BUSON
/RB5
AN4/C1INB/RB4
PGED3/AN3/C2INA/RPB3/RB3
PGEC3/AN2/CTCMP/C2INB/RPB2/CTED13/RB2
PGEC1/V
REF
-/AN1/RPB1/CTED12/RB1
PGED1/V
REF
+/AN0/RPB0/PMA6/RB0
PGEC2/AN6/RPB6/RB6
PGED2/AN7/RPB7/CTED3/RB7
AV
DD
AV
SS
AN8/RPB8/CTED10/RB8
AN9/RPB9/CTED4/PMA7/RB9
TMS/CV
REFOUT
/AN10/RPB10/CTED11/PMA13/RB10
TDO/AN11/PMA12/RB11
V
SS
V
DD
TCK/AN12/PMA11/RB12
TDI/AN13/PMA10/RB13
AN14/RPB14/SCK3/CTED5/PMA1/RB14
AN15/RPB15/OCFB/CTED6/PMA0/RB15
RPF4/SDA2/PMA9/RF4
RPF5/SCL2/PMA8/RF5
1:
2:
3:
4:
Full Pin Name
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
(4)
1
TQFP
Full Pin Name
USBID/RPF3/RF3
V
BUS
V
USB3V3
D-
D+
V
DD
OSC1/CLKI/RC12
OSC2/CLKO/RC15
V
SS
RPD8/RTCC/RD8
RPD9/SDA1/RD9
RPD10/SCL1/PMA15/RD10
RPD11/PMA14/RD11
RPD0/INT0/RD0
SOSCI/RPC13/RC13
SOSCO/RPC14/T1CK/RC14
AN24/RPD1/RD1
AN25/RPD2/SCK1/RD2
AN26/C3IND/RPD3/RD3
RPD4/PMWR/RD4
RPD5/PMRD/RD5
C3INC/RD6
C3INB/RD7
V
CAP
V
DD
C3INA/RPF0/RF0
RPF1/RF1
PMD0/RE0
PMD1/RE1
AN20/PMD2/RE2
RPE3/CTPLS/PMD3/RE3
AN21/PMD4/RE4
Pin #
The RPn pins can be used by remappable peripherals. See
Table 1
for the available peripherals and
Section 11.3 “Peripheral Pin
Select”
for restrictions.
Every I/O port pin (RBx-RGx) can be used as a change notification pin (CNBx-CNGx). See
Section 11.0 “I/O Ports”
for more information.
Shaded pins are 5V tolerant.
The metal plane at the bottom of the QFN device is not connected to any pins and is recommended to be connected to V
SS
externally.
DS60001290E-page 4
2014-2017 Microchip Technology Inc.
PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY
TABLE 4:
PIN NAMES FOR 100-PIN GENERAL PURPOSE DEVICES
100-PIN TQFP (TOP VIEW)
PIC32MX130F128L
PIC32MX150F256L
PIC32MX170F512L
100
1
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
Note
AN28/RG15
V
DD
AN22/RPE5/PMD5/RE5
AN23/PMD6/RE6
AN27/PMD7/RE7
AN29/RPC1/RC1
AN30/RPC2/RC2
AN31/RPC3/RC3
RPC4/CTED7/RC4
AN16/C1IND/RPG6/SCK2/PMA5/RG6
AN17/C1INC/RPG7/PMA4/RG7
AN18/C2IND/RPG8/PMA3/RG8
MCLR
AN19/C2INC/RPG9/PMA2/RG9
V
SS
V
DD
TMS/CTED1/RA0
AN32/RPE8/RE8
AN33/RPE9/RE9
AN5/C1INA/RPB5/RB5
AN4/C1INB/RB4
PGED3/AN3/C2INA/RPB3/RB3
PGEC3/AN2/CTCMP/C2INB/RPB2/CTED13/RB2
PGEC1/AN1/RPB1/CTED12/RB1
PGED1/AN0/RPB0/RB0
PGEC2/AN6/RPB6/RB6
PGED2/AN7/RPB7/CTED3/RB7
V
REF
-/PMA7/RA9
V
REF
+/PMA6/RA10
AV
DD
AV
SS
AN8/RPB8/CTED10/RB8
AN9/RPB9/CTED4/RB9
CV
REFOUT
/AN10/RPB10/CTED11/PMA13/RB10
AN11/PMA12/RB11
1:
2:
3:
Full Pin Name
Pin #
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
V
SS
V
DD
TCK/CTED2/RA1
AN34/RPF13/SCK3/RF13
AN35/RPF12/RF12
AN12/PMA11/RB12
AN13/PMA10/RB13
AN14/RPB14/CTED5/PMA1/RB14
AN15/RPB15/OCFB/CTED6/PMA0/RB15
V
SS
V
DD
AN36/RPD14/RD14
AN37/RPD15/SCK4/RD15
RPF4/PMA9/RF4
RPF5/PMA8/RF5
RPF3/RF3
AN38/RPF2/RF2
AN39/RPF8/RF8
RPF7/RF7
RPF6/SCK1/INT0/RF6
SDA1/RG3
SCL1/RG2
SCL2/RA2
SDA2/RA3
TDI/CTED9/RA4
TDO/RA5
V
DD
OSC1/CLKI/RC12
OSC2/CLKO/RC15
V
SS
RPA14/RA14
RPA15/RA15
RPD8/RTCC/RD8
RPD9/RD9
RPD10/PMA15/RD10
Full Pin Name
The RPn pins can be used by remappable peripherals. See
Table 1
for the available peripherals and
Section 11.3 “Peripheral Pin
Select”
for restrictions.
Every I/O port pin (RAx-RGx) can be used as a change notification pin (CNAx-CNGx). See
Section 11.0 “I/O Ports”
for more
information.
Shaded pins are 5V tolerant.
2014-2017 Microchip Technology Inc.
DS60001290E-page 5