Product
Folder
Sample &
Buy
Technical
Documents
Tools &
Software
Support &
Community
TPS54311, TPS54312, TPS54313
TPS54314, TPS54315, TPS54316
SLVS416C – FEBRUARY 2002 – REVISED JANUARY 2015
TPS5431x 3-V to 6-V Input, 3-A Output Synchronous Buck PWM Switcher With Integrated
FETs (SWIFT™)
1 Features
1
3 Description
As members of the SWIFT™ family of DC - DC
regulators, the TPS54311, TPS54312, TPS54313,
TPS54314, TPS54315 and TPS54316 low-input-
voltage high-outputcurrent synchronous-buck PWM
converters integrate all required active components.
Included on the substrate with the listed features are
a true, high performance, voltage error amplifier that
provides high performance under transient conditions;
an undervoltage-lockout circuit to prevent start-up
until the input voltage reaches 3 V; an internally and
externally set slow-start circuit to limit in-rush
currents; and a powergood output useful for
processor/logic reset, fault signaling, and supply
sequencing.
The TPS54311, TPS54312, TPS54313, TPS54314,
TPS54315 and TPS54316 devices are available in a
thermally enhanced 20-pin HTSSOP (PWP)
PowerPAD™ package, which eliminates bulky
heatsinks. TI provides evaluation modules and the
SWIFT designer software tool to aid in quickly
achieving high-performance power supply designs to
meet aggressive equipment development cycles.
Device Information
(1)
PART NUMBER
TPS54311
TPS54312
TPS54313
TPS54314
TPS54315
TPS54316
HTSSOP (20)
PACKAGE
OUTPUT VOLTAGE
0.9 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
•
•
•
•
•
•
•
60-mΩ, MOSFET Switches for High Efficiency at
3-A Continuous Output Source and Sink Current
0.9-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-V Fixed
Output Voltage Devices With 1.0% Initial Accuracy
Internally Compensated for Low Parts Count
Fast Transient Response
Wide PWM Frequency
−
Fixed 350 kHz, 550 kHz
or Adjustable 280 kHz to 700 kHz
Load Protected by Peak Current Limit and
Thermal Shutdown
Integrated Solution Reduces Board Area and
Total Cost
2 Applications
•
•
•
•
Low-Voltage, High-Density Systems With Power
Distributed at 5 V or 3.3 V
Point of Load Regulation for High Performance
DSPs, FPGAs, ASICs and Microprocessors
Broadband, Networking and Optical
Communications Infrastructure
Portable Computing/Notebook PCs
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Schematic
Input
VIN
PH
BOOT
PGND
Efficiency − %
Efficiency vs Load Current
Output
96
94
92
90
88
86
84
82
80
0
0.5
1
1.5
2
2.5
3
Load Current − A
T
A
= 25°C
V
I
= 5 V
V
O
= 3.3 V
TPS54316
VBIAS
VSENSE
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS54311, TPS54312, TPS54313
TPS54314, TPS54315, TPS54316
SLVS416C – FEBRUARY 2002 – REVISED JANUARY 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
Features
..................................................................
Applications
...........................................................
Description
.............................................................
Revision History.....................................................
Pin Configuration and Functions
.........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
Absolute Maximum Ratings ......................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Dissipation Ratings ...................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
1
1
1
2
3
4
4
4
4
4
5
7
7.4 Device Functional Modes........................................
12
8
Application and Implementation
........................
13
8.1 Application Information............................................
13
8.2 Typical Application .................................................
13
9 Power Supply Recommendations......................
16
10 Layout...................................................................
16
10.1 Layout Guidelines .................................................
16
10.2 Layout Example ....................................................
17
10.3 Thermal Considerations ........................................
17
11 Device and Documentation Support
.................
18
11.1
11.2
11.3
11.4
11.5
Documentation Support ........................................
Related Links ........................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
18
18
18
18
18
7
Detailed Description
..............................................
9
7.1 Overview ...................................................................
9
7.2 Functional Block Diagram .........................................
9
7.3 Feature Description...................................................
9
12 Mechanical, Packaging, and Orderable
Information
...........................................................
18
4 Revision History
Changes from Revision B (April 2005) to Revision C
•
Page
Added
Feature Description
section,
Device Functional Modes, Application and Implementation
section,
Power
Supply Recommendations
section,
Layout
section,
Device and Documentation Support
section, and
Mechanical,
Packaging, and Orderable Information
section. ....................................................................................................................
1
2
Submit Documentation Feedback
Copyright © 2002–2015, Texas Instruments Incorporated
Product Folder Links:
TPS54311 TPS54312 TPS54313 TPS54314 TPS54315 TPS54316
TPS54311, TPS54312, TPS54313
TPS54314, TPS54315, TPS54316
www.ti.com
SLVS416C – FEBRUARY 2002 – REVISED JANUARY 2015
5 Pin Configuration and Functions
PWP Package
20-Pin HTSSOP
Top View
AGND
VSENSE
NC
PWRGD
BOOT
PH
PH
PH
PH
PH
NC – No internal connection
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
RT
FSEL
SS/ENA
VBIAS
VIN
VIN
VIN
PGND
PGND
PGND
Pin Functions
PIN
NAME
AGND
BOOT
FSEL
NC
PGND
PH
PWRGD
RT
SS/ENA
VBIAS
VIN
VSENSE
NO.
1
5
19
3
11−13
6−10
4
20
18
17
14−16
2
DESCRIPTION
Analog ground. Return for compensation network/output divider, slow-start capacitor, VBIAS capacitor, RT resistor and FSEL pin. Make
PowerPAD connection to AGND.
Bootstrap input. 0.022-µF to 0.1-µF low-ESR capacitor connected from BOOT to PH generates floating drive for the high-side FET driver.
Frequency select input. Provides logic input to select between two internally set switching frequencies.
No connection
Power ground. High current return for the low-side driver and power MOSFET. Connect PGND with large copper areas to the input and
output supply returns, and negative terminals of the input and output capacitors.
Phase input/output. Junction of the internal high and low-side power MOSFETs, and output inductor.
Powergood open-drain output. Hi-Z when VSENSE
≥
90% V
ref
, otherwise PWRGD is low. Note that output is low when SS/ENA is low or
internal shutdown signal active.
Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency, f
s
.
Slow-start/enable input/output. Dual function pin which provides logic input to enable/disable device operation and capacitor input to
externally set the start-up time.
Internal bias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to AGND pin with a high quality, low
ESR 0.1-µF to 1.0-µF ceramic capacitor.
Input supply for the power MOSFET switches and internal bias regulator. Bypass VIN pins to PGND pins close to device package with a
high quality, low ESR 1-µF to 10-µF ceramic capacitor.
Error amplifier inverting input. Connect directly to output voltage sense point.
Copyright © 2002–2015, Texas Instruments Incorporated
Submit Documentation Feedback
3
Product Folder Links:
TPS54311 TPS54312 TPS54313 TPS54314 TPS54315 TPS54316
TPS54311, TPS54312, TPS54313
TPS54314, TPS54315, TPS54316
SLVS416C – FEBRUARY 2002 – REVISED JANUARY 2015
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
VIN, SS/ENA, SYNC
V
I
Input voltage
RT
VSENSE
BOOT
V
O
I
O
Output voltage
Source current
VBIAS, PWRGD, COMP
PH
PH
COMP, VBIAS
PH
I
S
Sink current
Voltage differential
T
J
T
stg
(1)
Storage temperature
COMP
SS/ENA, PWRGD
AGND to PGND
–40
−65
Operating virtual junction temperature
−0.3
−0.3
−0.3
−0.3
−0.3
−0.6
MAX
7
6
4
17
7
10
6
6
6
10
±0.3
125
150
UNIT
V
V
V
V
V
V
V
mA
A
mA
mA
V
°C
°C
Internally Limited
Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended
Operating Conditions.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
V
I
T
J
Input voltage range
Operating junction temperature
3
–40
MAX
6
125
UNIT
V
°C
6.3 Thermal Information
(1)
THERMAL METRIC
(2)
R
θJA
Junction-to-ambient thermal resistance
Junction-to-ambient thermal resistance (without solder on PowerPad)
(1)
TPS5431x
PWP (28 PINS)
26.0
57.5
UNIT
°C/W
(2)
Test board conditions:
(a) 3 inches × 3 inches, 2 layers, Thickness 0.062 inch
(b) 1.5 oz copper traces located on the top of the PCB
(c) 1.5 oz copper plane on the bottom of the PCB
(d) Ten thermal vias (see recommended land pattern)
For more information about traditional and new thermal metrics, see the
IC Package Thermal Metrics
application report,
SPRA953.
6.4 Dissipation Ratings
(1) (2)
PACKAGE
20-Pin PWP with solder
20-pin PWP without solder
(1)
(2)
T
A
= 25 °C
POWER RATING
3.85
(3)
1.73
T
A
= 70 °C
POWER RATING
2.12
0.96
T
A
= 85 °C
POWER RATING
1.54
0.69
UNIT
W
W
(3)
For more information on the PWP package, refer to TI technical brief,
SLMA002
Test board conditions:
(a) 3 inches × 3 inches, 2 layers, Thickness 0.062 inch
(b) 1.5 oz copper traces located on the top of the PCB
(c) 1.5 oz copper plane on the bottom of the PCB
(d) Ten thermal vias (see recommended land pattern)
Maximum power dissipation may be limited by overcurrent protection
4
Submit Documentation Feedback
Copyright © 2002–2015, Texas Instruments Incorporated
Product Folder Links:
TPS54311 TPS54312 TPS54313 TPS54314 TPS54315 TPS54316
TPS54311, TPS54312, TPS54313
TPS54314, TPS54315, TPS54316
www.ti.com
SLVS416C – FEBRUARY 2002 – REVISED JANUARY 2015
6.5 Electrical Characteristics
T
J
= –40°C to 125°C, VIN = 3 V to 6 V (unless otherwise noted)
PARAMETER
SUPPLY VOLTAGE, VIN
VIN
I
(Q)
Input voltage range
f
s
= 350 kHz, FSEL
≤
0.8 V, RT open
Quiescent current
f
s
= 550 kHz, FSEL
≤
2.5 V, RT open, Phase pin open
Shutdown, SS/ENA = 0 V
UNDERVOLTAGE LOCK OUT
Start threshold voltage
UVLO
Stop threshold voltage
Hysteresis voltage
Rising and falling edge deglitch
BIAS VOLTAGE
VBIAS
Output voltage
Output current
(2)
(1)
TEST CONDITIONS
MIN
3
TYP
MAX
6
UNIT
V
mA
6.2
8.4
1
2.95
2.70
0.14
2.80
0.16
2.5
9.6
12.8
1.4
3.0
V
V
V
µs
2.90
100
V
µA
I
(VBIAS)
= 0
2.70
2.80
OUTPUT VOLTAGE
TPS54311
TPS54312
TPS54313
V
O
Output voltage
TPS54314
TPS54315
TPS54316
REGULATION
Line regulation
(1) (3)
Load regulation
(1) (3)
OSCILLATOR
Internally set-free running frequency
FSEL
≤
0.8 V, RT open
FSEL
≥
2.5 V, RT open
RT = 180 kΩ (1% resistor to AGND)
(1)
Externally set-free running
frequency range
High level threshold voltage at
FSEL
Low level threshold voltage at FSEL
Ramp valley
(1)
T
J
= 25°C, VIN = 5 V
3 V
≤
VIN
≤
6 V, 0
≤
I
L
≤
3 A,
−40°C ≤
T
J
≤
125°C
T
J
= 25°C, VIN = 5 V
3 V
≤
VIN
≤
6 V, 0
≤
I
L
≤
3 A,
−40°C ≤
T
J
≤
125°C
T
J
= 25°C, VIN = 5 V
3 V
≤
VIN
≤
6 V, 0
≤
I
L
≤
3 A,
−40°C ≤
T
J
≤
125°C
T
J
= 25°C, VIN = 5 V
3 V
≤
VIN
≤
6 V, 0
≤
I
L
≤
3 A,
−40°C ≤
T
J
≤
125°C
T
J
= 25°C, VIN = 5 V
3 V
≤
VIN
≤
6 V, 0
≤
I
L
≤
3 A,
−40° ≤
T
J
≤
125°C
T
J
= 25°C, VIN = 5 V
4 V
≤
VIN
≤
6 V, 0
≤
I
L
≤
3 A,
−40° ≤
T
J
≤
125°C
I
L
= 3 A, 350
≤
fs
≤
550 kHz, T
J
= 85°C
I
L
= 0 A to 3 A, 350
≤
f
s
≤
550 kHz, T
J
= 85°C
280
440
252
460
663
2.5
−2.5%
–2.5%
–2.5%
–2.5%
–2.5%
–2.5%
0.9
2.5%
1.2
2.5%
1.5
2.5%
1.8
2.5%
2.5
2.5%
3.3
2.5%
0.21
0.21
350
550
280
500
700
420
660
308
540
762
V
V
V
V
V
V
%/V
%/A
kHz
RT = 100 kΩ (1% resistor to AGND)
RT = 68 kΩ (1% resistor to AGND)
(1)
kHz
V
0.8
0.75
1
200
V
V
V
ns
Ramp amplitude (peak-to-peak)
(1)
Minimum controllable on time
Maximum duty cycle
(1)
(1)
(2)
(3)
Specified by design
Static resistive loads only
Specified by the circuit used in
Figure 10.
(1)
90%
Copyright © 2002–2015, Texas Instruments Incorporated
Submit Documentation Feedback
5
Product Folder Links:
TPS54311 TPS54312 TPS54313 TPS54314 TPS54315 TPS54316
京公网安备 11010802033920号
EEWORLD
