16 Mbit (x16/x8) Concurrent SuperFlash Memory
SST34HF1601B
SST34HF1601B16Mb (x16/x8) Dual-bank CSF memory
Preliminary Specifications
FEATURES:
• Organized as 1M x16 or 2M x8
• Dual Bank Architecture for Concurrent
Read/Write Operation
– Bank1: 12 Mbit (768K x16/1536K x8) Flash
– Bank2: 4 Mbit (256K x16/512K x8) Flash
• Single 2.7-3.3V for Read and Write Operations
• Superior Reliability
– Endurance: 100,000 cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption:
– Active Current: 6 mA typical
– Standby Current: 4 µA typical
• Hardware Sector Protection/WP# Input Pin
– Protects 4 outermost blocks in the smaller bank
(128 KWord/256 KByte)
• Hardware Reset Pin (RST#)
• Sector-Erase Capability
– Uniform 1 KWord/2 KByte sectors
• Block-Erase Capability
– Uniform 32 KWord/64 KByte blocks
• Fast Read Access Time
– 80 ns
• Latched Address and Data
• Fast Erase and Word-Program (typical):
– Sector-Erase Time: 18 ms
– Block-Erase Time: 18 ms
– Chip-Erase Time: 70 ms
– Word-Program Time: 14 µs
– Byte-Program Time: 14 µs
– Chip Rewrite Time: 8 seconds (Word mode)
– Chip Rewrite Time: 16 seconds (Byte mode)
• Automatic Write Timing
– Internal V
PP
Generation
• End-of-Write Detection
– Toggle Bit
– Data# Polling
– Ready/Busy# pin
• CMOS I/O Compatibility
• JEDEC Standards
– Flash EEPROM Pinouts and command sets
• Packages Available
– 48-lead TSOP (12mm x 20mm)
– 56-ball TFBGA (8mm x 10mm)
PRODUCT DESCRIPTION
The SST34HF1601B consists of two memory banks,
Bank1 is 256K x16 or 512K x8 and Bank2 is 768K x16 or
1536K x8 which are CMOS concurrent Read/Write flash
memories manufactured with SST’s proprietary, high-per-
formance CMOS SuperFlash technology. The split-gate
cell design and thick-oxide tunneling injector attain better
reliability and manufacturability compared with alternate
approaches. The SST34HF1601B writes (Program or
Erase) with a 2.7-3.3V power supply. The SST34HF1601B
device conforms to JEDEC standard pin assignments for
x16/x8 memories.
Featuring
high-performance
Word-Program,
the
SST34HF1601B device provides a typical Word-Program
time of 14 µsec. The devices use Toggle Bit or Data# Poll-
ing to detect the completion of the Program or Erase opera-
tion. To protect against inadvertent writes, the
SST34HF1601B device has on-chip hardware and soft-
ware data protection schemes. Designed, manufactured,
and tested for a wide spectrum of applications, the
SST34HF1601B device is offered with a guaranteed
endurance of 10,000 cycles. Data retention is rated at
greater than 100 years.
The SST34HF1601B is suited for applications that require
convenient and economical updating of program, configu-
ration, or data memory. For all system applications, the
SST34HF1601B significantly improves performance and
reliability, while lowering power consumption. The
SST34HF1601B inherently uses less energy during Erase
and Program than alternative flash technologies. The total
energy consumed is a function of the applied voltage, cur-
rent, and time of application. Since for any given voltage
range, the SuperFlash technology uses less current to pro-
gram and has a shorter erase time, the total energy con-
sumed during any Erase or Program operation is less than
alternative flash technologies. The SST34HF1601B also
improves flexibility while lowering the cost for program,
data, and configuration storage applications.
©2003 Silicon Storage Technology, Inc.
S71244-01-000
11/03
1
The SST logo, SuperFlash, and FlashBank are registered trademarks of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
16 Mbit Concurrent SuperFlash Memory
SST34HF1601B
Preliminary Specifications
The SuperFlash technology provides fixed Erase and Pro-
gram times, independent of the number of Erase/Program
cycles that have occurred. Therefore the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose Erase
and Program times increase with accumulated Erase/Pro-
gram cycles.
To meet high density, surface mount requirements, the
SST34HF1601B is offered in 48-lead TSOP and 56-ball
BGA packages. See Figures 2 and 3 for pin assignments.
Read Operation
The Read operation of the SST34HF1601B is con-
trolled by CE# and OE#; both have to be low for the
system to obtain data from the outputs. CE# is used
for device selection. When CE# is high, the chip is
deselected and only standby power is consumed. OE#
is the output control and is used to gate data on the
output pins. The data bus is in high impedance state
when either CE# or OE# is high. Refer to the Read
cycle timing diagram for further details (Figure 4).
Device Operation
All memory banks share common I/O lines, WE# and OE#.
Memory bank selection is by bank select address (A
19
,
A
18
). WE# is used with SDP to control the Erase and Pro-
gram operations in each memory bank.
Commands are used to initiate the memory operation func-
tions of the device. Commands are written to the device
using standard microprocessor write sequences. A com-
mand is written by asserting WE# low while keeping CE#
low. The address bus is latched on the falling edge of WE#
or CE#, whichever occurs last. The data bus is latched on
the rising edge of WE# or CE#, whichever occurs first.
Word-Program Operation
The SST34HF1601B is programmed on a word-by-word
basis. Before programming, the sector where the word
exists must be fully erased. The Program operation con-
sists of three steps. The first step is the three-byte load
sequence for Software Data Protection. The second step
is to load word address and word data. During the Word-
Program operation, the addresses are latched on the fall-
ing edge of either CE# or WE#, whichever occurs last. The
data is latched on the rising edge of either CE# or WE#,
whichever occurs first. The third step is the internal Pro-
gram operation which is initiated after the rising edge of
the fourth WE# or CE#, whichever occurs first. The Pro-
gram operation, once initiated, will be completed typically
within 10 µs. See Figures 5 and 6 for WE# and CE# con-
trolled Program operation timing diagrams and Figure 18
for flowcharts. During the Program operation, the only valid
reads are Data# Polling and Toggle Bit. During the internal
Program operation, the host is free to perform additional
tasks. Any commands issued during the internal Program
operation are ignored.
After detecting the completion of
a Word-/Byte-Program operation (either through RY/
BY# line, Data# Polling, or Toggle Bit), the host must
keep CE# signal low for a minimum duration of Bus
Recovery Time (T
BR
= ~1 µs) before valid data can be
read correctly. Please see Figures 5 through 8 for cor-
responding AC timing diagrams.
Concurrent Read/Write Operation
Dual bank architecture of SST34HF1601B device allows
the concurrent Read/Write operation whereby the user can
read from one bank while programming or erasing in the
other bank. This operation can be used when the user
needs to read system code in one bank while updating
data in the other bank.
C
ONCURRENT
R
EAD
/W
RITE
S
TATE
Bank 1
Read
Read
Write
Write
No Operation
No Operation
Bank 2
No Operation
Write
Read
No Operation
Read
Write
Note:
For the purposes of this table, write means to perform Block-,
Sector-, or Chip-Erase or Word-Program operations as appli-
cable to the appropriate bank.
©2003 Silicon Storage Technology, Inc.
S71244-01-000
11/03
2
16 Mbit Concurrent SuperFlash Memory
SST34HF1601B
Preliminary Specifications
Sector- (Block-) Erase Operation
The Sector- (Block-) Erase operation allows the system to
erase the device on a sector-by-sector (or block-by-block)
basis. The SST34HF1601B offers both Sector-Erase and
Block-Erase mode. The sector architecture is based on
uniform sector size of 1 KWord/2 KByte. The Block-Erase
mode is based on uniform block size of 32 KWord/64
KByte. The Sector-Erase operation is initiated by executing
a six-byte command sequence with Sector-Erase com-
mand (30H) and sector address (SA) in the last bus cycle.
The Block-Erase operation is initiated by executing a six-
byte command sequence with Block-Erase command
(50H) and block address (BA) in the last bus cycle. The
sector or block address is latched on the falling edge of the
sixth WE# pulse, while the command (30H or 50H) is
latched on the rising edge of the sixth WE# pulse. The
internal Erase operation begins after the sixth WE# pulse.
See Figures 10 and 11 for timing waveforms. Any com-
mands issued during the Sector- or Block-Erase operation
are ignored.
this occurs, the system may possibly get an erroneous
result, i.e., valid data may appear to conflict with either DQ
7
or DQ
6
. In order to prevent spurious rejection, if an errone-
ous result occurs, the software routine should include a
loop to read the accessed location an additional two (2)
times. If both reads are valid, then the device has com-
pleted the Write cycle, otherwise the rejection is valid.
Ready/Busy# (RY/BY#)
The SST34HF1601B includes a Ready/Busy# (RY/BY#)
output signal. RY/BY# is actively pulled low while during an
internal Erase or Program operation is in progress. RY/BY#
is an open drain output that allows several devices to be
tied in parallel to V
DD
via an external pull up resistor. RY/
BY# is high impedance whenever CE# is high or RST# is
low. There is a 1 µs bus recovery time (T
BR
) required before
valid data can be read on the data bus. New commands
can be entered immediately after RY/BY# goes high.
Byte/Word (CIOF)
This device includes a CIOF pin to control whether the data
I/O pins operate as either x8 or x16. If the CIOF pin is at
logic ‘1’ (V
IH
) the device is in x16 data configuration; all data
I/O pins DQ
15
-DQ
0
are active and controlled by CE# and
OE#.
If the CIOF pin is at logic ‘0’, the device is in x8 data config-
uration; only data I/O pins DQ
7
-DQ
0
are active and con-
trolled by CE# and OE#. The remaining data pins DQ
14
-
DQ
8
are at High Z and pin DQ
15
is used as the Address
Input (A
-1
) for the least significant bit of the address bus.
Chip-Erase Operation
The SST34HF1601B provides a Chip-Erase operation,
which allows the user to erase all unprotected sectors/
blocks to the “1” state. This is useful when the device must
be quickly erased.
The Chip-Erase operation is initiated by executing a six-
byte command sequence with Chip-Erase command (10H)
at address 5555H in the last byte sequence. The Erase
operation begins with the rising edge of the sixth WE# or
CE#, whichever occurs first. During the Erase operation,
the only valid Read is Toggle Bit or Data# Polling. See
Table 4 for the command sequence, Figure 9 for timing dia-
gram, and Figure 21 for the flowchart. Any commands
issued during the Chip-Erase operation are ignored.
Data# Polling (DQ
7
)
When the SST34HF1601B is in the internal Program oper-
ation, any attempt to read DQ
7
will produce the comple-
ment of the true data. Once the Program operation is
completed, DQ
7
will produce true data. During internal
Erase operation, any attempt to read DQ
7
will produce a ‘0’.
Once the internal Erase operation is completed, DQ
7
will
produce a ‘1’. The Data# Polling is valid after the rising
edge of fourth WE# (or CE#) pulse for Program operation.
For Sector-, Block-, or Chip-Erase, the Data# Polling is
valid after the rising edge of sixth WE# (or CE#) pulse. See
Figure 7 for Data# Polling (DQ
7
) timing diagram and Figure
19 for a flowchart. There is a 1 µs bus recovery time (T
BR
)
required before valid data can be read on the data bus.
New commands can be entered immediately after DQ
7
becomes true data.
Write Operation Status Detection
The SST34HF1601B provides one hardware and two soft-
ware means to detect the completion of a Write (Program
or Erase) cycle, in order to optimize the system Write cycle
time. The hardware detection uses the Ready/Busy# (RY/
BY#) output pin. The software detection includes two sta-
tus bits: Data# Polling (DQ
7
) and Toggle Bit (DQ
6
). The
End-of-Write detection mode is enabled after the rising
edge of WE#, which initiates the internal Program or Erase
operation.
The actual completion of the nonvolatile write is asynchro-
nous with the system; therefore, either a Ready/Busy# (RY/
BY#), a Data# Polling (DQ
7
) or Toggle Bit (DQ
6
) read may
be simultaneous with the completion of the Write cycle. If
©2003 Silicon Storage Technology, Inc.
S71244-01-000
11/03
3
16 Mbit Concurrent SuperFlash Memory
SST34HF1601B
Preliminary Specifications
Toggle Bit (DQ
6
)
During the internal Program or Erase operation, any con-
secutive attempts to read DQ
6
will produce alternating 1s
and 0s, i.e., toggling between 1 and 0. When the internal
Program or Erase operation is completed, the DQ
6
bit will
stop toggling. The Toggle Bit is valid after the rising edge of
fourth WE# (or CE#) pulse for Program operation. For Sec-
tor-, Block- or Chip-Erase, the Toggle Bit is valid after the
rising edge of sixth WE# (or CE#) pulse. See Figure 8 for
Toggle Bit timing diagram and Figure 19 for a flowchart.
There is a 1 µs bus recovery time (T
BR
) required before
valid data can be read on the data bus. New commands
can be entered immediately after DQ
6
no longer toggles.
Hardware Reset (RST#)
The RST# pin provides a hardware method of resetting the
device to read array data. When the RST# pin is held low
for at least T
RP,
any in-progress operation will terminate and
return to Read mode (see Figure 15). When no internal
Program/Erase operation is in progress, a minimum period
of T
RHR
is required after RST# is driven high before a valid
Read can take place (see Figure 14).
The Erase operation that has been interrupted needs to be
reinitiated after the device resumes normal operation mode
to ensure data integrity.
Software Data Protection (SDP)
The SST34HF1601B provides the JEDEC standard Soft-
ware Data Protection scheme for all data alteration opera-
tions, i.e., Program and Erase. Any Program operation
requires the inclusion of the three-byte sequence. The
three-byte load sequence is used to initiate the Program
operation, providing optimal protection from inadvertent
Write operations, e.g., during the system power-up or
power-down. Any Erase operation requires the inclusion of
six-byte sequence. The SST34HF1601B is shipped with
the Software Data Protection permanently enabled. See
Table 4 for the specific software command codes. During
SDP command sequence, invalid commands will abort the
device to Read mode within T
RC.
The contents of DQ
15
-
DQ
8
can be V
IL
or V
IH
, but no other value during any SDP
command sequence.
Data Protection
The SST34HF1601B provides both hardware and software
features to protect nonvolatile data from inadvertent writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than 5
ns will not initiate a Write cycle.
V
DD
Power Up/Down Detection: The Write operation is
inhibited when V
DD
is less than 1.5V.
Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will inhibit the Write operation. This prevents inadvert-
ent writes during power-up or power-down.
Hardware Block Protection
The SST34HF1601B provides a hardware block protection
which protects the top 4 blocks of Bank 2, 128 KWord/256
KByte in the smaller bank. The block is protected when
WP# is held low. See Figure 1 for Block-Protection location.
A user can disable block protection by driving WP# high
thus allowing erase or program of data into the protected
sectors. WP# must be held high prior to issuing the write
command and remain stable until after the entire Write
operation has completed.
©2003 Silicon Storage Technology, Inc.
S71244-01-000
11/03
4
16 Mbit Concurrent SuperFlash Memory
SST34HF1601B
Preliminary Specifications
Product Identification
The Product Identification mode identifies the device and
manufacturer. For details, see Table 4 for software opera-
tion, Figure 12 for the Software ID Entry and Read timing
diagram and Figure 20 for the Software ID Entry command
sequence flowchart.
TABLE 1: P
RODUCT
I
DENTIFICATION
Word
Manufacturer’s ID
Device ID
SST34HF1601B
0001H
2762H
T1.0 1244
Product Identification Mode Exit
In order to return to the standard Read mode, the Software
Product Identification mode must be exited. Exit is accom-
plished by issuing the Software ID Exit command
sequence, which returns the device to the Read mode. This
command may also be used to reset the device to the Read
mode after any inadvertent transient condition that appar-
ently causes the device to behave abnormally, e.g., not
read correctly. Please note that the Software ID Exit com-
mand is ignored during an internal Program or Erase oper-
ation. See Table 4 for the software command code, Figure
13 for timing waveform and Figure 20 for a flowchart.
Data
00BFH
0000H
F
UNCTIONAL
B
LOCK
D
IAGRAM
Memory
Address
Address
Buffers
(4 KWord Sector Protection)
SuperFlash Memory
12 Mbit Bank
(x16/x8)
RST#
CIOF
CE#
WP#
WE#
OE#
RY/BY#
Control
Logic
SuperFlash Memory
4 Mbit Bank
(x16/x8)
I/O Buffers
DQ
15
- DQ
0
(A
-1
)
1244 B01.1
©2003 Silicon Storage Technology, Inc.
S71244-01-000
11/03
5
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