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V385GLF

Description
Line Driver, 5 Func, 5 Driver, CMOS, PDSO56, LEAD FREE, TSSOP-56
CategoryAnalog mixed-signal IC    Drivers and interfaces   
File Size90KB,9 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance
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V385GLF Overview

Line Driver, 5 Func, 5 Driver, CMOS, PDSO56, LEAD FREE, TSSOP-56

V385GLF Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerIDT (Integrated Device Technology)
Parts packaging codeTSSOP
package instructionROHS COMPLIANT, TSSOP-56
Contacts56
Reach Compliance Codeunknown
ECCN codeEAR99
Is SamacsysN
Differential outputYES
Number of drives5
Input propertiesSTANDARD
Interface integrated circuit typeLINE DRIVER
Interface standardsEIA-644; TIA-644
JESD-30 codeR-PDSO-G56
JESD-609 codee3
length14 mm
Humidity sensitivity level1
Number of functions5
Number of terminals56
Maximum operating temperature70 °C
Minimum operating temperature
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Encapsulate equivalent codeTSSOP56,.3,20
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)260
power supply3.3 V
Certification statusNot Qualified
Maximum receive delay
Maximum seat height1.2 mm
Maximum slew rate0.01 mA
Maximum supply voltage3.6 V
Minimum supply voltage3 V
Nominal supply voltage3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceMatte Tin (Sn) - annealed
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
width6.1 mm
Base Number Matches1
V385
8-B
IT
LVDS T
RANSMITTER FOR
V
IDEO
General Description
The V385 transmitter converts 28 bits of 3.3 V
CMOS/TTL into 4 Low Voltage Differential Signaling
(LVDS) data streams while the transmit clock input is
transmitted in parallel with the data streams over a fifth
LVDS link. The V385 can be programmed for rising
edge or falling edge clocks through pin R_FB.
ICS manufactures a large variety of video application
devices. Consult ICS for all of your video application
requirements.
Please refer to the V385A for new designs.
Features
Pin and function compatible with the National
DS90C385, TI SN65LVDS93 and THine
THC63LVDM83
Convert 28 bits of 3.3 V CMOS/TTL into 4 LVDS
streams
Up to 2.38 Gbps throughput or 297.5 Megabytes/sec
bandwidth
Pin Assignment
VCC
TxIN5
TxIN6
TxIN7
GND
TxIN8
TxIN9
TxIN10
VCC
TxIN11
TxIN12
TxIN13
GND
TxIN14
TxIN15
TxIN16
R_FB
TxIN17
TxIN18
TxIN19
GND
TxIN20
TxIN21
TxIN22
TxIN23
VCC
TxIN24
TxIN25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
TxIN4
TxIN3
TxIN2
GND
TxIN1
TxIN0
TxIN27
LVDS_GND
TxOUT0-
TxOUT0+
TxOUT1-
TxOUT1+
LVDS_VCC
LVDS_GND
TxOUT2-
TxOUT2+
TxCLKOUT-
TxCLKOUT+
TxOUT3-
TxOUT3+
LVDS_GND
PLL_GND
PLL_VCC
PLL_GND
PWRDWN
TxCLKIN
TxIN26
GND
Wide clock frequency range from 20 MHz to 85 MHz
Spread spectrum compatible
Supports VGA, SVGA, XGA, and SXGA
LVDS voltage swing of 350 mV for low EMI
On-chip PLL requires no external components
Single 3.3 V low-power CMOS design
Programmable rising or falling edge strobe
Power-down control function
Compatible with TIA/EIA-644 LVDS standards
Packaged in a 56-pin TSSOP (Pb free available)
Block Diagram
Red, Green, Blue
HSYNC
VSYNC
DATA ENABLE
CONTROL
TxOUT2-
R_FB
PWRDWN
CLOCK
PLL
TxCLKOUT-
TxOUT3+
TxOUT3-
TxCLKOUT+
TTL to
LVDS
TxOUT1-
TxOUT2+
24
TxOUT0+
TxOUT0-
TxOUT1+
56-pin TSSOP
V385 Datasheet
1
12/7/05
Revision 1.7
I n t e g r a t e d C i r c u i t S y s t e m s • 5 2 5 R a c e St r e e t , S a n J o s e , C A 9 5 1 2 6 • t e l ( 4 0 8) 2 97 - 1 2 0 1 • w ww. i c s t . co m
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