MOTOROLA
Designer's
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MMDF2C01HD/D
™
Data Sheet
Medium Power Surface Mount Products
Complementary TMOS
Field Effect Transistors
MMDF2C01HD
Motorola Preferred Device
MiniMOS™ devices are an advanced series of power MOSFETs
which utilize Motorola’s High Cell Density HDTMOS process.
These miniature surface mount MOSFETs feature ultra low RDS(on)
and true logic level performance. They are capable of withstanding
high energy in the avalanche and commutation modes and the
drain–to–source diode has a very low reverse recovery time.
MiniMOS devices are designed for use in low voltage, high speed
switching applications where power efficiency is important. Typical
applications are dc–dc converters, and power management in
portable and battery powered products such as computers,
printers, cellular and cordless phones. They can also be used for
low voltage motor controls in mass storage products such as disk
drives and tape drives.
•
Ultra Low RDS(on) Provides Higher Efficiency and Extends
Battery Life
•
Logic Level Gate Drive — Can Be Driven by Logic ICs
•
Miniature SO–8 Surface Mount Package — Saves Board Space
•
Diode Is Characterized for Use In Bridge Circuits
•
Diode Exhibits High Speed, With Soft Recovery
•
IDSS Specified at Elevated Temperature
•
Mounting Information for SO–8 Package Provided
™
COMPLEMENTARY
DUAL TMOS POWER FET
2.0 AMPERES
12 VOLTS
RDS(on) = 0.045 OHM
(N–CHANNEL)
RDS(on) = 0.18 OHM
(P–CHANNEL)
D
N–Channel
G
S
D
P–Channel
CASE 751–05, Style 14
SO–8
N–Source
N–Gate
G
S
P–Source
P–Gate
1
2
3
4
8
7
6
5
N–Drain
N–Drain
P–Drain
P–Drain
Top View
MAXIMUM RATINGS
(TJ = 25°C unless otherwise noted)(1)
Rating
Drain–to–Source Voltage
Gate–to–Source Voltage
Drain Current — Continuous
— Pulsed
N–Channel
P–Channel
N–Channel
P–Channel
N–Channel
P–Channel
Symbol
VDSS
VGS
ID
IDM
TJ and Tstg
PD
R
θJA
TL
Value
20
12
±
8.0
5.2
3.4
48
17
– 55 to 150
2.0
62.5
260
Unit
Vdc
Vdc
A
Operating and Storage Temperature Range
Total Power Dissipation @ TA= 25°C (2)
Thermal Resistance — Junction to Ambient (2)
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds.
°C
Watts
°C/W
°C
DEVICE MARKING
D2C01
(1) Negative signs for P–Channel device omitted for clarity.
(2) Mounted on 2” square FR4 board (1” sq. 2 oz. Cu 0.06” thick single sided) with one die operating, 10 sec. max.
ORDERING INFORMATION
Device
MMDF2C01HDR2
Reel Size
13″
Tape Width
12 mm embossed tape
Quantity
2500 units
Designer’s Data for “Worst Case” Conditions
— The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
HDTMOS and MiniMOS are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
Preferred
devices are Motorola recommended choices for future use and best overall value.
REV 5
©
Motorola TMOS Power MOSFET Transistor Device Data
Motorola, Inc. 1996
1
MMDF2C01HD
ELECTRICAL CHARACTERISTICS
(TA = 25°C unless otherwise noted)(1)
Characteristic
OFF CHARACTERISTICS
Drain–Source Breakdown Voltage
(VGS = 0 Vdc, ID = 250
µAdc)
Zero Gate Voltage Drain Current
(VGS = 0 Vdc, VDS = 20 Vdc)
(VGS = 0 Vdc, VDS = 12 Vdc)
Gate–Body Leakage Current
(VGS =
±
8.0 Vdc, VDS = 0)
ON CHARACTERISTICS(2)
Gate Threshold Voltage
(VDS = VGS, ID = 250
µAdc)
Drain–to–Source On–Resistance
(VGS = 4.5 Vdc, ID = 4.0 Adc)
(VGS = 4.5 Vdc, ID = 2.0 Adc)
Drain–to–Source On–Resistance
(VGS = 2.7 Vdc, ID = 2.0 Adc)
(VGS = 2.7 Vdc, ID = 1.0 Adc)
Forward Transconductance
(VDS = 2.5 Adc, ID = 2.0 Adc)
(VDS = 2.5 Adc, ID = 1.0 Adc)
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Transfer Capacitance
SWITCHING CHARACTERISTICS(3)
Turn–On Delay Time
Rise Time
Turn–Off Delay Time
Fall Time
Turn–On Delay Time
Rise Time
Turn–Off Delay Time
Fall Time
Total Gate Charge
Gate–Source Charge
Gate–Drain Charge
(VDS = 10 Vdc, ID = 4.0 Adc,
VGS = 4.5 Vdc)
(VDS = 6.0 Vdc, ID = 2.0 Adc,
VGS = 4.5 Vdc)
(VDS = 6.0 Vdc, ID = 4.0 Adc,
VGS = 4.5 Vdc,
RG = 2.3
Ω)
(VDS = 6.0 Vdc, ID = 2.0 Adc,
VGS = 4.5 Vdc,
RG = 6.0
Ω)
(VDD = 6.0 Vdc, ID = 4.0 Adc,
VGS = 2.7 Vdc,
RG = 2.3
Ω)
(VDD = 6.0 Vdc, ID = 2.0 Adc,
VGS = 2.7 Vdc,
RG = 6.0
Ω)
td(on)
tr
td(off)
tf
td(on)
tr
td(off)
tf
QT
Q1
Q2
Q3
(1) Negative signs for P–Channel device omitted for clarity.
(2) Pulse Test: Pulse Width
≤
300
µs,
Duty Cycle
≤
2%.
(3) Switching characteristics are independent of operating junction temperature.
(N)
(P)
(N)
(P)
(N)
(P)
(N)
(P)
(N)
(P)
(N)
(P)
(N)
(P)
(N)
(P)
(N)
(P)
(N)
(P)
(N)
(P)
(N)
(P)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
13
21
60
156
20
38
29
68
10
16
42
44
24
68
28
54
9.2
9.3
1.3
0.8
3.5
4.0
3.0
3.0
26
45
120
315
40
75
58
135
20
35
84
90
48
135
56
110
13
13
—
—
—
—
—
—
(continued)
nC
ns
(VDS = 10 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
Ciss
Coss
Crss
(N)
(P)
(N)
(P)
(N)
(P)
—
—
—
—
—
—
425
530
270
410
115
177
595
740
378
570
230
250
pF
V(BR)DSS
IDSS
(N)
(P)
IGSS
—
—
—
100
—
—
—
—
1.0
1.0
nAdc
(N)
(P)
20
12
—
—
—
—
Vdc
µAdc
Symbol
Polarity
Min
Typ
Max
Unit
VGS(th)
RDS(on)
(N)
(P)
(N)
(P)
0.7
0.7
—
—
—
—
3.0
3.0
0.8
1.0
0.035
0.16
0.043
0.2
6.0
4.75
1.1
1.1
0.045
0.18
Vdc
Ohm
RDS(on)
(N)
(P)
gFS
(N)
(P)
—
—
0.055
0.22
Ohm
mhos
2
Motorola TMOS Power MOSFET Transistor Device Data
MMDF2C01HD
ELECTRICAL CHARACTERISTICS — continued
(TA = 25°C unless otherwise noted)(1)
Characteristic
SOURCE–DRAIN DIODE CHARACTERISTICS
(TC = 25°C)
Forward Voltage(2)
(IS = 4.0 Adc, VGS = 0 Vdc)
(IS = 2.0 Adc, VGS = 0 Vdc)
Reverse Recovery Time
Symbol
Polarity
Min
Typ
Max
Unit
VSD
trr
ta
(N)
(P)
(N)
(P)
(N)
(P)
(N)
(P)
(N)
(P)
—
—
—
—
—
—
—
—
—
—
0.95
1.69
38
48
17
23
22
25
0.028
0.05
1.1
2.0
—
—
—
—
—
—
—
—
Vdc
ns
(IF = IS,
dIS/dt = 100 A/µs)
Reverse Recovery Stored Charge
(1) Negative signs for P–Channel device omitted for clarity.
(2) Pulse Test: Pulse Width
≤
300
µs,
Duty Cycle
≤
2%.
tb
QRR
µC
TYPICAL ELECTRICAL CHARACTERISTICS
N–Channel
8
I D , DRAIN CURRENT (AMPS)
4.5 V
3.1 V
6 2.7 V
2.3 V
2.5 V
VGS = 8 V
2.1 V
4
TJ = 25°C
I D , DRAIN CURRENT (AMPS)
3
VGS = 8 V
4.5 V
3.1 V
2.7 V
2.1 V
2
1.9 V
1
1.7 V
1.5 V
1.6
1.8
2
0
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
2.5 V
2.3 V
TJ = 25°C
P–Channel
4
1.9 V
1.7 V
2
1.5 V
1.3 V
0
0
0.2
0.4
0.6
0.8
1
1.2
1.4
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 1. On–Region Characteristics
Figure 1. On–Region Characteristics
8
I D , DRAIN CURRENT (AMPS)
VDS
≥
10 V
I D , DRAIN CURRENT (AMPS)
4
VDS
≥
10 V
6
3
4
100°C
25°C
2
100°C
1
2
TJ = – 55°C
25°C
TJ = – 55°C
0
1
1.2
1.4
1.6
1.8
2
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
2.2
0
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
2.8
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
Figure 2. Transfer Characteristics
Figure 2. Transfer Characteristics
Motorola TMOS Power MOSFET Transistor Device Data
3
MMDF2C01HD
TYPICAL ELECTRICAL CHARACTERISTICS
N–Channel
RDS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS)
RDS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS)
0.07
TJ = 25°C
ID = 2 A
0.06
0.35
TJ = 25°C
ID = 1 A
P–Channel
0.30
0.25
0.05
0.20
0.04
0.15
0.03
0
6
2
4
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
8
0.1
0
6
2
4
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
8
Figure 3. On–Resistance versus
Gate–To–Source Voltage
RDS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS)
RDS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS)
Figure 3. On–Resistance versus
Gate–To–Source Voltage
0.050
TJ = 25°C
0.045
VGS = 2.7 V
0.30
TJ = 25°C
0.25
0.040
0.20
VGS = 2.7 V
0.035
4.5 V
4.5 V
0.15
0.030
0
2
6
4
ID, DRAIN CURRENT (AMPS)
8
0.10
0
0.8
1.6
2.4
ID, DRAIN CURRENT (AMPS)
3.2
4
Figure 4. On–Resistance versus Drain Current
and Gate Voltage
Figure 4. On–Resistance versus Drain Current
and Gate Voltage
RDS(on) , DRAIN–TO–SOURCE RESISTANCE
(NORMALIZED)
1.5
VGS = 4.5 V
ID = 4 A
RDS(on) , DRAIN–TO–SOURCE RESISTANCE
(NORMALIZED)
2
2
VGS = 4.5 V
ID = 2 A
1.5
1
1
0.5
0.5
0
– 50
– 25
0
25
50
75
100
125
150
0
– 50
– 25
0
25
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 5. On–Resistance Variation with
Temperature
Figure 5. On–Resistance Variation with
Temperature
4
Motorola TMOS Power MOSFET Transistor Device Data
MMDF2C01HD
TYPICAL ELECTRICAL CHARACTERISTICS
N–Channel
100
VGS = 0 V
TJ = 125°C
I DSS , LEAKAGE (nA)
I DSS , LEAKAGE (nA)
TJ = 125°C
100
1000
VGS = 0 V
P–Channel
10
100°C
10
0
6
2
4
8
10
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
12
0
4
8
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
12
Figure 6. Drain–To–Source Leakage
Current versus Voltage
Figure 6. Drain–To–Source Leakage
Current versus Voltage
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (∆t) are deter-
mined by how fast the FET input capacitance can be charged
by current from the generator.
The published capacitance data is difficult to use for calculat-
ing rise and fall because drain–gate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that
t = Q/IG(AV)
During the rise and fall time interval when switching a resis-
tive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG – VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn–on and turn–off delay times, gate current is
not constant. The simplest calculation uses appropriate val-
ues from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG – VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off–state condition when cal-
culating td(on) and is read at a voltage corresponding to the
on–state when calculating td(off).
At high switching speeds, parasitic circuit elements com-
plicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a func-
tion of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to mea-
sure and, consequently, is not specified.
The resistive switching time variation versus gate resis-
tance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely op-
erated into an inductive load; however, snubbing reduces
switching losses.
Motorola TMOS Power MOSFET Transistor Device Data
5
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