Single Output Clock Generator
IDT5V926A
DATA SHEET
FEATURES:
• 3V to 3.6V operating voltage
• 48MHz to 160MHz output frequency range
• Input from fundamental crystal oscillator or external
source
• Internal PLL feedback (loading the feedback output
relative to the other outputs, will adjust the propagation
delay between REF inputs and outputs)
• Select inputs (S
[1:0]
) for FB divide selection (multiply
ratio of 2, 3, 4, 4.25, 5, 6, 6.25, and 8)
• Low jitter
• PLL bypass for testing and power-down control
(S1 = H, S0 = H, powers part down <500µA)
• Available in TSSOP package
• Pin and function compatible to IDT5V926
DESCRIPTION:
The IDT5V926A is a low-cost, low skew, low jitter, and
high-performance clock multiplier with a reference clock
from either a lower frequency crystal or clock input. It has
been specially designed to interface with Gigabit Ethernet
and Fast Ethernet applications by providing a 125MHz
clock from 25MHz input. It can be programmed to provide
output frequencies ranging from 48MHz to 160MHz, with
input frequencies ranging from 6MHz to 80MHz.
The IDT5V926A includes an internal RC filter that pro-
vides excellent jitter characteristics and eliminates the
need for external components. When using the optional
crystal input, the device accepts a 10 - 40MHz fundamental
mode crystal with a maximum equivalent series resistance
of 50Ω.
APPLICATIONS:
•
•
•
•
•
•
Gigabit ethernet
Router
Network switches
SAN
Instrumentation
Fibre channel
FUNCTIONAL BLOCK DIAGRAM
OE
VCO DIVIDE
1/N
PHASE
DETECTOR
CHARGE
PUMP
LOOP
FILTER
VCO
Q
OUT
0
1
X1/REF
CRYSTAL
OSCILLATOR
X2
SELECT MODE
Q
REF
S1
S0
REFE
IDT5V926A REVISION A JUNE 11, 2009
1
©2009
Integrated Device Technology, Inc.
IDT5V926A Data Sheet
SINGLE OUTPUT CLOCK GENERATOR
PIN CONFIGURATION
REFE
X
1
/REF
X
2
V
DD
V
DDQ
GND
Q
REF
V
DDQ
1
2
3
4
5
6
7
8
TSSOP
TOP VIEW
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Parameter
Supply Voltage to Ground
Input Voltage
Output Current
Storage Temperature
Junction Temperature
Max.
-0.5 to +4.6
-0.5 to +4.6
±50
-65 to +150
150
Unit
V
V
mA
°C
°C
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9
S
0
S
1
OE
GND
V
DDQ
GND
Q
OUT
V
DDQ
V
DD/
V
DDQ
V
I
I
O
T
STG
T
J
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
PIN DESCRIPTION
Pin Name
S[1:0]
OE
REFE
X1/REF
Type Description
I
I
I
I
I
O
O
PWR
PWR
PWR
Three level divider/mode select pins. Float to MID.
Output enable bar. Outputs Qout and QREF are in a high-impedance state when
HIGH. Set OE LOW for normal operation (has internal pull-down).
QREF enable input. QREF stopped LOW when HIGH. When set REFE LOW, the
QREF is enabled (has internal pull-down).
Crystal oscillator input or clock input.
Crystal oscillator output. Leave unconnected for clock input.
Output at N*REF frequency.
Output at REF frequency.
Power supply for the device outputs. Connect to VDD on PCB.
Power supply for the device core and inputs. Connect to VDD on PCB.
Ground supply.
CRYSTAL SPECIFICATION
The crystal oscillators should be fundamental mode quartz
crystals: overtone crystals are not suitable. Crystal frequency
should be specified for parallel resonance with 50Ω maximum
equivalent series resonance. Crystal tuning capacitors should
be connected from X1/REF to GND and from X2 to GND.
X2
QOUT
QREF
VDDQ
VDD
GND
DIVIDE SELECTION TABLE
(1)
S1
L
L
L
M
M
M
H
H
H
S0
L
M
H
L
M
H
L
M
H
Divide-by-N Value
2
3
4
4.25
5
6
6.25
8
TEST
Mode
PLL
PLL
PLL
PLL
PLL
PLL
PLL
PLL
TEST (2)
NOTES:
1. H = HIGH, M = MID, L = LOW
2. Test mode for low frequency testing. In this mode, REF clock bypasses the VCO (VCO powered down) and the crystal oscillator is powered down.
DT5V926A REVISION A JUNE 11, 2009
2
©2009
Integrated Device Technology, Inc.
IDT5V926A Data Sheet
SINGLE OUTPUT CLOCK GENERATOR
COMMON OUTPUT FREQUENCY EXAMPLES (MHz)
Output
Input
FB Divide Selection S[1:0]
48
24
LL
60
10
MH
64
16
LH
72
12
MH
75
25
LM
80
10
HM
90
15
MH
100
20
MM
Output
Input
FB Divide Selection S[1:0]
106.25
17
HL
106.25
25
ML
120
15
HM
125
20
HL
125
25
MM
125
62.5
LL
150
25
MH
155.52
19.44
HM
OPERATING CONDITIONS
Symbol
V
DD
/V
DDQ
T
A
C
IN
Parameter
Power Supply Voltage
Operating Temperature
Input Capacitance, OE, F = 1MHz, V
IN
= 0V, T
A
= 25°C
Min.
3
- 40
—
Typ.
3.3
25
5
Max.
3.6
+85
Unit
V
°C
pF
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: T
A
= –40°C to +85°C, V
DD
/V
DDQ
= 3.3V ±0.3V
Symbol
V
IL
V
IH
V
IHH
V
IMM
V
ILL
I
3
I
IH
V
OL
V
OH
Parameter
Input LOW Voltage
Input HIGH Voltage
Input HIGH Voltage
Input MID Voltage
Input LOW Voltage
3-Level Input DC Current, S
[1:0]
Input HIGH Current
Output LOW Voltage
Output HIGH Voltage
Test Conditions
Min.
—
2
V
DD
- 0.6
V
DD
/2 - 0.3
—
—
- 50
- 200
—
—
—
2.4
Typ.
—
—
—
—
—
—
—
—
—
2
—
—
Max
0.8
—
—
V
DD
/2 + 0.3
0.6
+200
+50
—
100
4
0.4
—
Unit
V
V
V
V
V
μA
μA
mA
V
V
3-level input only
3-level input only
3-level input only
V
IN
= V
DD
V
IN
= V
DD
/2
V
IN
= GND
V
IN
= V
DD
V
IN
= V
DD
, S
[1:0]
= HH
I
OL
= 12mA
I
OH
= -12mA
HIGH Level
MID Level
LOW Level
OE, REFE
X
1
/REF
DT5V926A REVISION A JUNE 11, 2009
3
©2009
Integrated Device Technology, Inc.
IDT5V926A Data Sheet
SINGLE OUTPUT CLOCK GENERATOR
POWER SUPPLY CHARACTERISTICS
Symbol
I
DD_PD
Parameter
Power Down Current
Test Conditions
(1)
V
DD
= Max.
S
[1:0]
= HH
OE = L
;
X
1
/REF = L
All outputs unloaded
ΔI
DD
I
DD
Supply Current per Input
Dynamic Supply Current
V
DD
= Max., V
IN
= 3V
V
DD
= 3.6V
S
[1:0]
= LL
OE = L
F
OUT
= 160MHz
All outputs unloaded
NOTE:
1. For conditions shown as Min. or Max., use the appropriate values specified under DC Electrical Characteristics.
Min.
—
Typ.
—
Max
500
Unit
μA
—
—
—
—
30
50
μA
mA
AC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Symbol
Parameter
Rise Time, Fall Time
Test Conditions
0.8V to 2V
Min.
Typ.
0.7
0.7
45
44
40
Max.
1.5
2.0
55
56
60
100
90
125
48
160
MHz
ps
%
Unit
ns
t
R,
t
F
d
T
Q
OUT
Q
REF
Q
OUT < 125MHz
Q
OUT > 125MHz
Q
REF
Output/Duty Cycle
V
T
=
V
DDQ
/2
F
OUT
= 106.25MHz
t
J
f
OUT
Cycle - Cycle Jitter
F
OUT
= 125MHz
F
OUT
= 155.52MHz
Output Frequency
INPUT TIMING REQUIREMENTS
Symbol
t
R,
t
F
t
PWC
D
H
f
OSC
f
IN
NOTES:
1. Where pulse width implied by D
H
is less than the t
PWC
limit, t
PWC
limit applies.
2. When using a clock input.
Description
(1)
Maximum input rise and fall time, 0.8V to 2V
(2)
Input clock pulse, HIGH or LOW
(2)
Input duty cycle
(2)
XTAL oscillator frequency
Input frequency
(2)
Min.
—
2
10
10
48/N
Max.
10
—
90
40
160/N
Unit
ns/V
ns
%
MHz
MHz
DT5V926A REVISION A JUNE 11, 2009
4
©2009
Integrated Device Technology, Inc.
IDT5V926A Data Sheet
SINGLE OUTPUT CLOCK GENERATOR
P
ARAMETER
M
EASUREMENT
I
NFORMATION
1.65V±0.15V
V
DD
,
V
DDQ
SCOPE
QOUT
LVCMOS
GND
tcycle
n
➤
tjit(cc)
=
|
tcycle
n –
tcycle
n+1
|
1000 Cycles
-1.65V±0.15V
3.3V C
ORE
/3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
C
YCLE
-
TO
-C
YCLE
J
ITTER
2V
0.8V
t
R
2V
0.8V
t
F
QREF,
QOUT
t
PW
t
PERIOD
QREF,
QOUT
odc =
t
PW
t
PERIOD
O
UTPUT
R
ISE
/F
ALL
T
IME
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
DT5V926A REVISION A JUNE 11, 2009
5
©2009
Integrated Device Technology, Inc.
➤
V
DD
➤
Qx
tcycle
n+1
➤
2
x 100%
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