EP1S40F1020C5N datasheet, PDF - EEWORLD Datasheet

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EP1S40F1020C5N: Descriptionfpga - field programmable gate array fpga - stratix I 4125 labs 773 ios; CategoryProgrammable logic devices Programmable logic; File Size10MB，864 Pages; ManufacturerAltera (Intel); Environmental Compliance

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fpga - field programmable gate array fpga - stratix I 4125 labs 773 ios

EP1S40F1020C5N Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Parts packaging code	BGA
package instruction	BGA, BGA1020,31X31,50
Contacts	1020
Reach Compliance Code	compli
ECCN code	3A001.A.7.A
JESD-30 code	S-PBGA-B1020
JESD-609 code	e1
length	33 mm
Humidity sensitivity level	3
Configurable number of logic blocks	4697
Number of entries	818
Number of logical units	41250
Output times	818
Number of terminals	1020
Maximum operating temperature	85 °C
Minimum operating temperature
organize	4697 CLBS
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA1020,31X31,50
Package shape	SQUARE
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	245
power supply	1.5,1.5/3.3 V
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Maximum seat height	3.5 mm
Maximum supply voltage	1.575 V
Minimum supply voltage	1.425 V
Nominal supply voltage	1.5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL EXTENDED
Terminal surface	TIN SILVER COPPER
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	40
width	33 mm
Base Number Matches	1

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Stratix Device Handbook, Volume 1

101 Innovation Drive

San Jose, CA 95134

(408) 544-7000

http://www.altera.com

S5V1-3.4

Contents

Chapter Revision Dates .......................................................................... vii

About This Handbook .............................................................................. ix

How to Find Information ........................................................................................................................ ix

How to Contact Altera ............................................................................................................................. ix

Typographic Conventions ........................................................................................................................ x

Section I. Stratix Device Family Data Sheet

Revision History ............................................................................................................................ Part I–1

Chapter 1. Introduction

Introduction ............................................................................................................................................ 1–1

Features ................................................................................................................................................... 1–2

Chapter 2. Stratix Architecture

Functional Description .......................................................................................................................... 2–1

Logic Array Blocks ................................................................................................................................ 2–3

LAB Interconnects ............................................................................................................................ 2–4

LAB Control Signals ......................................................................................................................... 2–5

Logic Elements ....................................................................................................................................... 2–6

LUT Chain & Register Chain .......................................................................................................... 2–8

addnsub Signal ................................................................................................................................. 2–8

LE Operating Modes ........................................................................................................................ 2–8

Clear & Preset Logic Control ........................................................................................................ 2–13

MultiTrack Interconnect ..................................................................................................................... 2–14

TriMatrix Memory ............................................................................................................................... 2–21

Memory Modes ............................................................................................................................... 2–22

Clear Signals .................................................................................................................................... 2–24

Parity Bit Support ........................................................................................................................... 2–24

Shift Register Support .................................................................................................................... 2–25

Memory Block Size ......................................................................................................................... 2–26

Independent Clock Mode .............................................................................................................. 2–44

Input/Output Clock Mode ........................................................................................................... 2–46

Read/Write Clock Mode ............................................................................................................... 2–49

Single-Port Mode ............................................................................................................................ 2–51

Multiplier Block .............................................................................................................................. 2–57

Adder/Output Blocks ................................................................................................................... 2–61

Modes of Operation ....................................................................................................................... 2–64

Altera Corporation

iii

Contents

Stratix Device Handbook, Volume 1

DSP Block Interface ........................................................................................................................ 2–70

PLLs & Clock Networks ..................................................................................................................... 2–73

Global & Hierarchical Clocking ................................................................................................... 2–73

Enhanced & Fast PLLs ................................................................................................................... 2–81

Enhanced PLLs ............................................................................................................................... 2–87

Fast PLLs ........................................................................................................................................ 2–100

I/O Structure ...................................................................................................................................... 2–104

Double-Data Rate I/O Pins ......................................................................................................... 2–111

External RAM Interfacing ........................................................................................................... 2–115

Programmable Drive Strength ................................................................................................... 2–119

Open-Drain Output ...................................................................................................................... 2–120

Slew-Rate Control ........................................................................................................................ 2–120

Bus Hold ........................................................................................................................................ 2–121

Programmable Pull-Up Resistor ................................................................................................ 2–122

Advanced I/O Standard Support .............................................................................................. 2–122

Differential On-Chip Termination ............................................................................................. 2–127

MultiVolt I/O Interface ............................................................................................................... 2–129

High-Speed Differential I/O Support ............................................................................................ 2–130

Dedicated Circuitry ...................................................................................................................... 2–137

Byte Alignment ............................................................................................................................. 2–140

Power Sequencing & Hot Socketing ............................................................................................... 2–140

Chapter 3. Configuration & Testing

IEEE Std. 1149.1 (JTAG) Boundary-Scan Support ............................................................................ 3–1

SignalTap II Embedded Logic Analyzer ............................................................................................ 3–5

Configuration ......................................................................................................................................... 3–5

Operating Modes .............................................................................................................................. 3–5

Configuring Stratix FPGAs with JRunner .................................................................................... 3–7

Configuration Schemes ................................................................................................................... 3–7

Partial Reconfiguration .................................................................................................................... 3–7

Remote Update Configuration Modes .......................................................................................... 3–8

Stratix Automated Single Event Upset (SEU) Detection ................................................................ 3–12

Custom-Built Circuitry .................................................................................................................. 3–13

Software Interface ........................................................................................................................... 3–13

Temperature Sensing Diode ............................................................................................................... 3–13

Chapter 4. DC & Switching Characteristics

Operating Conditions ........................................................................................................................... 4–1

Power Consumption ........................................................................................................................... 4–17

Timing Model ....................................................................................................................................... 4–19

Preliminary & Final Timing .......................................................................................................... 4–19

Performance .................................................................................................................................... 4–20

Internal Timing Parameters .......................................................................................................... 4–22

External Timing Parameters ......................................................................................................... 4–33

Stratix External I/O Timing .......................................................................................................... 4–36

I/O Timing Measurement Methodology .................................................................................... 4–60

External I/O Delay Parameters .................................................................................................... 4–66

Altera Corporation

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