Integrated
Circuit
Systems, Inc.
Preliminary Information
M926-02
VCSO B
ASED
C
LOCK
G
ENERATOR
P
IN
A
SSIGNMENT
(9 x 9 mm SMT)
XTAL_1 / REF_IN
GND
STOP
EXT_CLK
EN_EXT_CLK
FOUT_SEL
nFOUT3
FOUT3
VCC
XTAL_2
FOUT4
nFOUT4
FOUT5
nFOUT5
VCC
DNC
DNC
DNC
27
26
25
24
23
22
21
20
19
G
ENERAL
D
ESCRIPTION
The M926-02 is a PLL (Phase Locked Loop) based
clock generator that uses an
internal VCSO (Voltage Controlled
SAW Oscillator) to produce a very
low jitter output clock. From the
M926-02-622.0800
, an output clock
frequency of
622.08
or
155.52
MHz
is provided from six LVPECL clock
output pairs. (Other frequencies
are available; consult factory.) The accuracy of the
output frequency is assured by the internal PLL that
phase-locks the internal VCSO to the reference input
frequency (
19.44
MHz for the
M926-02-622.0800
). The input
reference can either be an external crystal, utilizing the
internal crystal oscillator, or a stable external clock
source such as a packaged crystal oscillator.
28
29
30
31
32
33
34
35
36
M926-02
(Top View)
18
17
16
15
14
13
12
11
10
nFOUT2
FOUT2
nFOUT1
FOUT1
GND
nFOUT0
FOUT0
VCC
GND
F
EATURES
◆
Output clock frequency range 150MHz to 700MHz
(
For other output frequencies, consult factory)
◆
Selectable divider chooses one of two frequencies
◆
Six identical LVPECL output pairs (same frequency)
◆
Jitter 0.5ps rms (@622.08MHz, over 12kHz-20MHz)
◆
Ideal for OC-48/STM-16 clock reference
◆
Output-to-output skew < 100ps
◆
External XTAL or LVCMOS reference input
◆
Selectable external feed-through clock input
◆
STOP
clock control (Logic 1 stops output clocks)
◆
Integrated SAW (surface acoustic wave) delay line
◆
Single 3.3V power supply
◆
Small 9 x 9 mm SMT (surface mount) package
Figure 1: Pin Assignment
Example Output Frequency Configurations
(
M926-02-622.0800
)
Ref Clock
Frequency
(MHz)
19.44
VCSO
Frequency
(MHz)
622.08
P Divider
Value
1
4
Output
Frequency
(MHz)
622.08
155.52
Table 1: Example Output Frequency Configurations
S
IMPLIFIED
B
LOCK
D
IAGRAM
M926-02-622.08 (Other Frequencies Available)
VSCO
External
Crystal
or
Reference
Clock Input
(19.44MHz)
GND
GND
GND
OP_IN
nOP_OUT
nVC
VC
OP_OUT
nOP_IN
1
2
3
4
5
6
7
8
9
XTAL
OSC
Frequency
Multiplying
PLL
Divider
O
1
LVPECL
Output
Clock
Pairs
(155.52 or
77.76MHz)
External
Loop Filter
Divider
Select
External
Clock
Input
External
Clock
Select
Output
Clock STOP
Control
Figure 2: Simplified Block Diagram
M926-02 Datasheet Rev 0.5
M926-02 VCSO Based Clock Generator
Revision 013003
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M926-02
VCSO B
ASED
C
LOCK
G
ENERATOR
Preliminary Information
D
ETAILED
B
LOCK
D
IAGRAM
R
LOOP
C
LOOP
R
POST
C
POST
C
POST
R
LOOP
C
LOOP
OP_OUT
R
POST
nOP_OUT
nVC
VC
External
Loop Filter
Components
M926-02
Phase
Detector
OP_IN
nOP_IN
XTAL_1 / REF_IN
XTAL_2
R
IN
SAW Delay Line
FOUT5
nFOUT5
FOUT4
nFOUT4
O
1
XTAL
OSC
R
IN
Loop Filter
Amplifier
Phase
Shifter
VCSO
P Divider
P = 1 or 4
FOUT3
nFOUT3
FOUT2
nFOUT2
FOUT1
nFOUT1
FOUT0
nFOUT0
M Divider
M = 32
Phase Locked Loop (PLL)
EXT_CLK
EN_EXT_CLK
STOP
FOUT_SEL
Figure 3: Detailed Block Diagram
P
IN
D
ESCRIPTIONS
Number
1,2,3,10,14,26
4,9
5,8
6, 7
11,19,33
12,13
15,16
17,18
20,21
29,30
31,32
22
23
24
25
27
28
34,35,36
Name
GND
OP_IN, nOP_IN
nOP_OUT, OP_OUT
nVC, VC
VCC
FOUT0, nFOUT0
FOUT1, nFOUT1
FOUT2, nFOUT2
FOUT3, nFOUT3
FOUT4, nFOUT4
FOUT5, nFOUT5
FOUT_SEL
EN_EXT_CLK
EXT_CLK
STOP
XTAL_1 / REF_IN
XTAL_2
DNC
I/O
Configuration
Description
Ground
Input
Output
Input
Power
Power supply ground.
Used for external loop filter. See
Figure 4.
Power supply connection, connect to +
3.3
V
Output
No internal terminator
Clock output pairs, differential LVPECL output
(
622.08
or
155.52
MHz for the
M926-02-622.0800
)
Determines post-PLL divider value:
When
FOUT_SEL
=
0
, P =
1
When
FOUT_SEL
=
1
, P =
4
Logic
1
enables the
EXT_CLK
input.
Use Logic
0
for normal operation.
External clock feed-through: 0 to 200 MHz
Logic
1
stops clock outputs.
Use Logic
0
for normal operation.
External crystal connection. Also accepts
LVCMOS/LVTTL compatible clock source.
External crystal connection. Leave unconnected
when driving pin
27
with external clock reference.
Do Not Connect. Internal test pins.
Table 2: Pin Descriptions
Input
Input
Input
Input
Input
Input
Internal pull-down
resistor
1
Internal pull-down
resistor
1
Note 1: For typical value of internal pull-down resistor, see
DC Characteristics, Pull-down
on
pg. 5
for typical value.
M926-02 Datasheet Rev 0.5
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M926-02
VCSO B
ASED
C
LOCK
G
ENERATOR
Preliminary Information
For the
M926-02-622.0800
(see
“Ordering Information”
on
pg. 6):
F
UNCTIONAL
D
ESCRIPTION
The M926-02 is a PLL (Phase Locked Loop) based
clock generator that generates output clocks
synchronized to an input reference clock.
The M926-02 combines the flexibility of a VCSO
(Voltage Controlled SAW Oscillator) with the stability of
a crystal oscillator.
Input Reference
The
19.44
MHz input reference can either be an external,
discrete crystal device or a stable external clock source
such as a packaged crystal oscillator:
•
VCSO output frequency =
622.08
MHz
•
M =
32
•
Input reference frequency =
19.44
MHz
Therefore, for the
M926-02-622.0800
:
622.08
MHz =
32
×
19.44
MHz
The VCSO center output frequency of
622.08
MHz
enables the product of
M
×
input crystal frequency
to fall within the lock range of the VCSO.
Post-PLL Divider
The M926-02 also features a post-PLL divider (labeled
“P Divider”) for selecting one of two output frequencies
(e.g., 622.08 or 155.52 MHz).
The
FOUT_SEL
pin determines the P Divider value:
•
If an external crystal is used with the on-chip crystal
oscillator circuit (XTAL OSC), the external crystal
should be a parallel-resonant, fundamental mode
crystal. Apply it to the
XTAL_1 / REF_IN
and
XTAL_2
input
pins. External crystal load capacitors are also
required.
•
If an external LVCMOS/LVTTL clock source is used,
apply it to the
XTAL_1 / REF_IN
input pin.
In either case, the reference clock is supplied directly to
the phase detector of the PLL.
The
EX_CLK
pin is available for a clock feed-through
mode for testing. See
“External Clock Feed-through”
on
pg. 4.
•
When
FOUT_SEL
=
0
, P =
1
.
•
When
FOUT_SEL
=
1
, P =
4
.
External Loop Filter
To provide stable PLL operation, and thereby a low jitter
output clock, the M926-02 requires the use of an
external loop filter. This is provided via the provided
filter pins (see
Figure 4).
Due to the differential signal path design, the
implementation requires two identical complementary
RC filters as shown here.
R
LOOP
C
LOOP
R
POST
C
POST
C
POST
R
LOOP
OP_IN
4
9
The PLL
The PLL (Phase Locked Loop) includes the phase
detector, the VCSO, and a feedback divider (labeled
“M Divider”).
The feedback divider is a digital circuit that divides the
VCSO output frequency by a numerical value “M” in
order to match the input reference frequency.
By controlling the frequency and phase of the VCSO,
the phase detector precisely locks the frequency and
phase of the feedback divider output to that of the input
reference. This creates an output frequency that is a
multiple of the reference frequency (which is output
from the VCSO).
The relationship between the VCSO output frequency,
the M Divider, and the input reference frequency is
defined as follows:
Fvcso = M
×
Fxtal
C
LOOP
OP_OUT
8
5
R
POST
nOP_OUT
nVC
6
7
nOP_IN
VC
Figure 4: External Loop Filter
External Loop Filter Component Values
PLL
Damping
Bandwidth Factor
395
Hz
1.2
kHz
10
kHz
1
2.0
2.9
2.4
R loop
1.5
kΩ
4.7
kΩ
39.0
kΩ
C loop
4.70
µF
1.00
µF
0.01
µF
R post
20
kΩ
20
kΩ
20
kΩ
C post
3300
pF
1000
pF
240
pF
Table 3: External Loop Filter Component Values
Note 1: Recommended for most applications
M926-02 Datasheet Rev 0.5
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External Clock Feed-through
The
EXT_CLK
pin provides an input for an external
single-ended clock that directly drives the LVPECL
clock outputs. In application, this may be used for
system debugging and performance evaluation.
1. Set pin
EN_EXT_CLK
to Logic 1.
2. Apply an external LVCMOS/LVTTL clock source
to the
EXT_CLK
input pin.
Due to the fact that EXT_CLK bypasses the PLL,
any frequency between DC and 200MHz can be
used.
M926-02
VCSO B
ASED
C
LOCK
G
ENERATOR
Preliminary Information
STOP Clock
The
STOP
pin puts the output clock into a static condition.
Logic 1 Output clocks are static
Logic 0 Output clocks enabled for normal operation
A
BSOLUTE
M
AXIMUM
R
ATINGS1
Symbol Parameter
Rating
Unit
V
I
V
O
V
CC
T
S
Inputs
Outputs
Power Supply Voltage
Storage Temperature
-
0.5
to V
CC
+
0.5
-
0.5
to V
CC
+
0.5
4.6
V
-
45
to +
100
o
C
Table 4: Absolute Maximum Ratings
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the
device. These ratings ard stress specifications only. Functional operation of product at these conditions
or any conditions beyond those listed in
Recommended Conditions of Operation, DC Characteristics,
or
AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
R
ECOMMENDED
C
ONDITIONS OF
O
PERATION
Symbol Parameter
Min
3.135
0
Typ
3.3
Max
3.465
Unit
V
CC
T
A
Positive Supply Voltage
Ambient Operating Temperature
V
o
C
+
70
Table 5: Recommended Conditions of Operation
M926-02 Datasheet Rev 0.5
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●
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Integrated
Circuit
Systems, Inc.
M926-02
VCSO B
ASED
C
LOCK
G
ENERATOR
Preliminary Information
E
LECTRICAL
S
PECIFICATIONS
DC Characteristics
Unless stated otherwise, V
CC
= 3.3 Volts + 5%, T
A
= 0
o
C to 70
o
C, Output Frequency=622.08MHz
1
, Outputs terminated with 50Ω to V
CC
- 2V
Symbol Parameter
Min
3.135
Typ
3.3
300
Max
3.465
Unit
Power Supply
V
CC
I
CC
Positive Supply Voltage
Power Supply Current
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
FOUT_SEL,
Input Capacitance, All Inputs
EN_EXT_CLK, EXT_CLK,
STOP, XTAL_1 / REF_IN
EN_EXT_CLK, STOP
XTAL_1 / REF_IN
(XTAL_2 disconnected)
FOUT_SEL, EN_EXT_CLK,
EXT_CLK, STOP
V
mA
Logic Inputs
V
IH
V
IL
I
IH
I
IL
2
V
cc
+
0.3
0.8
150
V
V
µA
µA
-
0.3
-
5.0
(V
cc
/ 2 ) +
0.5
V
cc
+
0.3
Reference
Clock
Input
V
IH
V
IL
I
IH
I
IL
V
µA
µA
-
0.3
-
5.0
(V
cc
/ 2 ) +
0.5
V
150
All Inputs
Pull-down
Differential
Output
C
IN
4
51
V
cc
-
1.4
V
cc
-
1.0
V
cc
-
1.7
0.85
pF
kΩ
V
V
V
R
pulldown
Internal Pull-down Resistor
V
OH
V
OL
V
P
-
P
Output High Voltage
Output Low Voltage
Peak to Peak Output Voltage
FOUT, nFOUT (0-5)
V
cc
-
2.0
0.6
Note 1: For other VCSO center frequencies, contact ICS
Table 6: DC Characteristics
AC Characteristics
Unless implied otherwise, V
CC
= 3.3 Volts + 5%, T
A
= 0
o
C to 70
o
C, Output Frequency=622.08MHz
1
, Outputs terminated with 50Ω to V
CC
- 2V
Symbol Parameter
Min
150
Typ
Max
700
Unit
Test Conditions
FOUT_SEL
=0
1
F
OUT
F
IN
APR
Φn
Output Frequency Range
Nominal Input Frequency,
XTAL_1 / REF_IN
VCSO Pull-Range
Single Side Band
Phase Noise
@622.08MHz
Jitter (rms)
Output Duty Cycle, High Time
Output Rise Time
Output Fall Time
Output Skew
EXT_CLK
Frequency
FOUT, nFOUT (0-5)
FOUT, nFOUT (0-5)
1
kHz Offset
10
kHz Offset
100
kHz Offset
MHz
MHz
ppm
dBc/Hz
dBc/Hz
dBc/Hz
ps
%
ps
ps
ps
MHz
19.44
+
100
+
150
-
100
-
110
-
134
0.5
1.0
55
350
350
100
J(t)
t
DC
t
R
t
F
t
S
12
kHz to
20
MHz
45
200
200
50
275
275
20
% to
80
%
20
% to
80
%
Between Any Pair
EXT_CLK
0
200
Note 1: For other VCSO center frequencies, contact ICS
Table 7: AC Characteristics
M926-02 Datasheet Rev 0.5
Integrated Circuit Systems, Inc.
●
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