Continuous Data Transfer (CDT) architecture eliminates
wait states between read and write operations
Supports 40MHz to 133MHz bus operations
Internally self-timed output buffer control eliminates the
need for synchronous output enable
Registered inputs and outputs for pipelined operation
Single 2.5V to 3.3V supply
Clock-to-output time
- Clk to Q = 7ns
Clock Enable (CEN) pin to enable clock and suspend
operation
Synchronous self-timed writes
Three Chip Enables (CS0, CS1, CS2) for simple depth
expansion
"ZZ" Sleep Mode option for partial power-down
"SHUTDOWN" Mode option for deep power-down
Four Word Burst Capability--linear or interleaved
Operational Environment
- Total Dose: 100 krad(Si)
- SEL Immune:
≤
100MeV-cm
2
/mg
- SEU error rate: 1.7x10
-6
errors/bit-day
Package options:
- 288-lead CLGA, CCGA, and CBGA
Standard Microelectronics Drawing (SMD) 5962-15213
- QMLQ and Q+ pending
INTRODUCTION
The UT8SP2M48 is a high performance 100,663,296-bit
synchronous static random access memory (SSRAM) device
that is organized as 2M words of 48 bits. This device is
equipped with three chip selects (CS0, CS1, and CS2), a write
enable (WE), and an output enable (OE) pin, allowing for
significant design flexibility without bus contention. The
device supports a four word burst function using (ADV_LD).
All synchronous inputs are registered on the rising edge of the
clock provided the Clock Enable (CEN) input is enabled LOW.
Operations are suspended when CEN is disabled HIGH and the
previous operation is extended. Write operation control signals
are WE and six byte write enables BWE[5:0]. All write
operations are performed by internal self-timed circuitry.
For easy bank selection, three synchronous Chip Enables
(CS0, CS1, CS2) and an asynchronous Output Enable (OE)
provide for output tri-state control. The output drivers are
synchronously tri-stated during the data portion of a write
sequence to avoid bus contention.
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ADDR
CMD
User Command Interface Logic
CLK
Housekeeping,
and Fault Logic
Main Memory Array 2Meg x 48
Write
Address and
Command
Queue
Write Data
Coherency Logic
Write Data
Steering Logic
Stall Cycle
Registers
Pipeline
Register
Write Data
Queue
Read Data
Steering and
Fault Logic
D
IN
Q
OUT
Figure 1. UT8SP2M48 Block Diagram
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Table 1: Pin Definitions
NAME
CS0
CS1
CS2
A[20:0]
BWE[5:0]
WE
DESCRIPTION
Chip Enable 0, Input, Active LOW:
Sampled on the rising edge of CLK.
Used in conjunction with CS1 and CS2 to select or deselect the device.
Chip Enable 1 Input, Active HIGH:
Sampled on the rising edge of CLK.
Used in conjunction with CS0 and CS2 to select or deselect the device.
Chip Enable 2 Input, Active LOW:
Sampled on the rising edge of CLK.
Used in conjunction with CS0 and CS1 to select or deselect the device.
Address Inputs:
Sampled at the rising edge of the CLK. A[1:0] is fed to the
two-bit burst counter.
Byte Write Enable, Active LOW:
Qualified with WE, allows writes to each
of six bytes of memory when active, and masks input data when disabled.
Write Enable Input, Active LOW:
Sampled on the rising edge of CLK if
CEN is active LOW. This signal must be enabled LOW to initiate a write
sequence.
Advance/Load Input:
Advances the on-chip address counter or loads a new
address. When HIGH (and CEN is enabled LOW) the internal burst counter
is advanced. When LOW, a new address can be loaded into the device for an
access. After deselection, drive ADV_LD LOW to load a new address.
Clock Input:
Used to capture all synchronous inputs to the device. CLK is
qualified with CEN. CLK is only recognized if CEN is active LOW.
Output Enable, Asynchronous Input, Active LOW:
Combined with the
synchronous logic block inside the device to control the direction of the I/O
pins. When LOW, the I/O pins are enabled to behave as outputs. When
disabled HIGH, I/O pins are tri-stated, and act as input data pins. OE is
masked during the data portion of a write sequence, during the first clock
when emerging from a deselected state and when the device is deselected.
Clock Enable Input, Active LOW:
When enabled LOW, the clock signal is
recognized by the SSRAM. When deasserted HIGH, the clock signal is
masked. Because deasserting CEN does not deselect the device, CEN can be
used to extend the previous cycle when required.
Bidirectional Data I/Os:
As inputs, DQ[47:0] feed into an on-chip data
register that is triggered by the rising edge of CLK. As outputs, DQ[47:0]
delivers the data contained in the memory location specified by the addresses
presented during the previous clock rise of the read cycle. The direction of
the pins is controlled by OE. When OE is enabled LOW, the pins behave as
outputs. When HIGH, DQs are placed in a tri-state condition. The outputs
are automatically tri-stated during the data portion of a write sequence,
during the first clock when emerging from a deselected state, and when the
device is deselected, regardless of the state of OE. Aeroflex recommends
connecting all DQ pins to either VDDQ or VSS through a >10kΩ resistor.
Reset Input, Active Low:
Resets device to known configuration. Reset is
required at initial power-up, after exiting shutdown mode, or after any power
interruption.
TYPE
Input-Synchronous
Input-Synchronous
Input-Synchronous
Input-Synchronous
Input-Synchronous
Input-Synchronous
ADV_LD
Input-Synchronous
CLK
OE
Input-Clock
Input-Asynchronous
CEN
Input-Synchronous
DQ[47:0]
I/O-Synchronous
RESET
Input-ASynchronous
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Table 1: Pin Definitions
NAME
ZZ
DESCRIPTION
ZZ “Sleep” Input, Active HIGH:
When HIGH, places the device in a non-
time critical “sleep” condition with data integrity preserved. During normal
operation, this pin must be LOW.
Shutdown Input, Active HIGH:
When HIGH, places device in shutdown
mode. System clock can be stopped. Memory contents are not retained.
Device Ready Output:
READY outputs a HIGH when device is available
for normal operations. READY outputs a LOW when requesting an idle
cycle or during power up initialization.
Mode Input:
Established at power up. Selects the burst order of the device.
When tied to VSS selects linear burst sequence. When tied to VDDQ selects
interleaved burst sequence.
Input Current Reference:
Provided for external precision current reference
resistor connection.
Operating Frequency Range Selection Input:
Input should be HIGH for
CLK input above 80MHz, LOW for CLK input at 80MHz and below. DC
input and CLK frequency can only be changed during sleep mode or
established at power on.
Power supply inputs to the core of the device.
Power supply for the I/O circuitry.
Ground inputs to the core of the device.
Ground for I/O circuitry.
Not used Input Low:
Pins designated as NUIL need to be externally
connected by user to V
SSQ
through a >10kΩ±10% resistor.
Not used Input High:
Pins designated as NUIH need to be externally
connected by user to V
DDQ
through a >10kΩ±10% resistor.
No Connects.
Not internally connected to the die.
JTAG Circuit Serial Data Output:
Package pin requires a pull-up through
>10kΩ±10% resistor to V
DDQ
.
JTAG Circuit Serial Data Input:
Device pin internally connected through
a 75kΩ±10% resistor to V
DDQ
.
JTAG Controller Test Mode Select:
Device pin internally connected
through a 75kΩ±10% resistor to V
DDQ
.
JTAG Circuit Clock Input:
Package pin requires a pull-up through
>10kΩ±10% resistor to V
DDQ
.
TYPE
Input-Synchronous
SHUTDOWN
READY
1
Input-Asynchronous
Output-Synchronous
MODE
2
Input-DC
EXTRES
2
FREQSEL
Input-DC
Input-DC
V
DD
V
DDQ
V
SS
V
SSQ
NUIL
NUIH
NC
TDO
3
TDI
3
TMS
3
TCK
3
Power Supply
I/O Power Supply
Ground
I/O Ground
--
--
---
JTAG Serial Output
Synchronous
JTAG Serial Input
Synchronous
Test Mode Select
Synchronous
JTAG Clock
Note:
1. Reference application note AN-MEM-004 for additional READY signal information.
2. DC inputs are established at power up and cannot be switched while power is applied to the device.
3. Reference application note AN-MEM-005 for JTAG operations. JTAG operations are intended for terrestrial use and not guaranteed in radiation environment.
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DEVICE OPERATION
The UT8SP2M48 is synchronous-pipelined SSRAM designed
specifically to eliminate wait states during Write/Read or Read/
Write transitions. All synchronous inputs and outputs are
registered on the rising edge of clock. The clock signal is enabled
by the Clock Enable input (CEN). When CEN is HIGH, the clock
signal is disregarded and all internal states are maintained. All
synchronous operations are qualified by CEN. Once power-up
requirements have been satisfied, the input clock may only be
stopped during sleep (ZZ is HIGH) or shutdown mode
(SHUTDOWN is HIGH). Maximum access delay from the
rising edge of clock (t
CQV
) is 7ns (133 MHz device).
Access is initiated by asserting all three Chip Enables
(CS0, CS1, CS2) active at the rising edge of the clock with
Clock Enable (CEN) and ADV_LD asserted LOW. The
address presented to the device will be registered. Access can
be either a Read or Write operation, depending on the status of
the Write Enable (WE).
Write operations are initiated by the Write Enable (WE) input.
All write commands are controlled by built in synchronous
self-timed circuitry.
Three synchronous Chip Enables (CS0, CS1, CS2) and an
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