V827565N24SBJZ-D3 datasheet, PDF

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V827565N24SBJZ-D3: DescriptionSynchronous DRAM Module, 128MX72, 0.7ns, CMOS, PDMA184; Categorystorage storage; File Size243KB，16 Pages; ManufacturerProMOS Technologies Inc

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V827565N24SBJZ-D3 Overview

Synchronous DRAM Module, 128MX72, 0.7ns, CMOS, PDMA184

V827565N24SBJZ-D3 Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Objectid	1125506626
Reach Compliance Code	compliant
ECCN code	EAR99
Maximum access time	0.7 ns
Maximum clock frequency (fCLK)	200 MHz
I/O type	COMMON
JESD-30 code	R-PDMA-N184
memory density	9663676416 bit
Memory IC Type	SYNCHRONOUS DRAM MODULE
memory width	72
Number of terminals	184
word count	134217728 words
character code	128000000
Maximum operating temperature	70 °C
Minimum operating temperature
organize	128MX72
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	DIMM
Encapsulate equivalent code	DIMM184
Package shape	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	2.5 V
Certification status	Not Qualified
refresh cycle	8192
Maximum standby current	0.18 A
Maximum slew rate	6.48 mA
Nominal supply voltage (Vsup)	2.5 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	NO LEAD
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED

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V827565N24SB

1GB 184-PIN DDR REGISTERED ECC DIMM

128M x 72

Features

■

184 Pin Registered 134,217,728 x 72 bit

Organization DDR SDRAM Modules

■

Utilizes High Performance 128M x 4 DDR

SDRAM in TSOPII and FBGA Package

■

Single +2.5V (± 0.2V) Power Supply

Single +2.6V (± 0.1V) Power Supply for DDR400

■

Programmable CAS Latency, Burst Length, and

Wrap Sequence (Sequential & Interleave)

■

Auto Refresh (CBR) and Self Refresh

■

All Inputs, Outputs are SSTL-2 Compatible

■

8192 Refresh Cycles every 64 ms

■

Serial Presence Detect (SPD)

■

DDR SDRAM Performance

Component Used

-6

-7

Module Speed

Description

The V827565N24SB memory module is

organized 134,217,728 x 72 bits in a 184 pin

memory module. The 128M x 72 memory module

uses 18 ProMOS 128M x 4 DDR SDRAM. The x72

modules are ideal for use in high performance

computer systems where increased memory

density and fast access times are required.

-75

-8

(PC400B)

166

(PC333)

133

(PC266B)

Units

MHz

CLK

Clock Frequency

166

143

133

125

Clock Frequency (max.)

(PC266A) (PC266B)

200

(PC333)

(PC200)

(max.)

Clock Access Time

7.5

Clock Cycle Time CAS Latency = 3

CAS Latency = 2.5

Clock Cycle Time CAS Latency = 2.5

RCD

tRCD parameter

7.5

Module Speed

tRP parameter

A1 t

PC1600 (100MHz @ CL2)

PC2100B (133MHz @ CL2.5)

PC2100A (133MHz @ CL2)

PC2700 (166MHz @ CL2.5)

V827565N24SB Rev. 1.0 October 2005

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