V827565K24SA
1GB 184-PIN DDR UNBUFFERED ECC DIMM
128M x 72
Features
■
184 Pin Unbuffered 134,217,728 x 72 bit
Organization DDR SDRAM Modules
■
Utilizes High Performance 64M x 8 DDR
SDRAM in TSOPII Packages
■
Single +2.5V (± 0.2V) Power Supply
■
Single +2.6V (± 0.1V) Power Supply for DDR400
■
Programmable CAS Latency, Burst Length, and
Wrap Sequence (Sequential & Interleave)
■
Auto Refresh (CBR) and Self Refresh
■
All Inputs, Outputs are SSTL-2 Compatible
■
8196 Refresh Cycles every 64 ms
■
Serial Presence Detect (SPD)
■
DDR SDRAM Performance
Component Used
-6
Module Speed
t
CK
t
AC
Description
The V827565K24SA memory module is
organized 134,217,728 x 72 bits in a 184 pin
memory module. The 128M x 72 memory module
uses 18 ProMOS 64M x 8 DDR SDRAM. The x72
modules are ideal for use in high performance
computer systems where increased memory
density and fast access times are required.
-7
-75
D3
(PC400B)
-8
C0
166
(PC333)
Units
MHz
ns
ns
ns
CLK
CLK
Clock Frequency
166
143
133
125
Clock Frequency (max.)
200
(PC333) (PC266A) (PC266B) (PC200)
(max.)
7.5
7.5
6
5
3
3
8
Clock Access Time
6
7
Clock Cycle Time CAS Latency = 2
CAS Latency = 2.5
t
CK
Clock Cycle Time CAS Latency = 2.5
Clock Cycle Time CAS Latency = 3
7.5
6
6
3
3
t
RCD
t
RP
tRCD parameter
tRP parameter
V827565K24SA Rev. 1.1 March 2008
1
ProMOS TECHNOLOGIES
Part Number Information
V827565K24SA
V
ProMOS
8
2
7 5
DATA WIDTH
& COMP DENSITY
65 X64 using 128M
66 X64 using 256M
67 X64 using 512M
6 5
DATA
DEPTH
K
2
4
S
A
T
G
PCB TYPE
-
D
3
G : LEAD PLATING_GOLD
REFRESH
RATE
0: 4K
1: 2K
2: 8K
3: 1K
COMPONENT PKG
LEAD
LEAD
GREEN
PACKAGE
DESCRIPTION
I
J
M
TI
SI
TSOP
60-Ball FBGA
BGA
Die-Stacked TSOP
Die-Stacked FBGA
COMPONENT
REV LEVEL
L : LEAD PLATING_LOW PROFILE
W : LEAD FREE_GOLD
X : LEAD FREE_LOW PROFILE
Y : GREEN_GOLD
Z : GREEN_LOW PROFILE
TYPE
8
DDR
68 X64 using 1G
69 X64 using 2G
6A X64 using stacked 512M (256M die)
6B X64 using stacked 1G (256M die)
72 X72 using 64M
9 DDRII
BANKS
2 : 2 Banks
4 : 4 Banks
8 : 8 Banks
PLATING FREE
T
S
B
TS
E
F
H
TE
SF
VOLTAGE
2: 2.5 V
1: 1.8V
73 X72 using 128M
74 X72 using 256M
75 X72 using 512M
76 X72 using 1G
77 X72 using 2G
7A X72 using stacked 512M (256M die)
7B X72 using stacked 1G (256M die)
MODULE TYPE & COMP WIDTH
BASED ON
184PIN UNBUFFERED
184PIN REGISTERED
200PIN SODIMM
172PIN MicroDIMM
DDR2 UNBUFFERED
DDR2 REGISTERED
A4
C4
A6
C6
X4
I
N
V
X16
J
O
B
X8
K
U
G
M
A8
C8
I/O INTERFACE
S: SSTL_2
Q: SSTL _18
SS
SPEED
B0 :
B1 :
C0 :
D0 :
D1 :
D3 :
D4 :
PC2100B (133MHz @CL2.5-3-3)
PC2100A (133MHz @CL2-2-2)
PC2700 (166MHz @CL2.5-3-3)
PC3200 (200MHz @CL2.5-3-3)
PC3200 (200MHz @CL2-2-2)
PC3200 (200MHz @CL3-3-3)
PC3200 (200MHz @CL3-4-4)
V827565K24SA Rev. 1.1 March 2008
2
ProMOS TECHNOLOGIES
Block Diagram
CS1
CS0
DQS0
DM0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
V827565K24SA
DQS4
DM4
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
DQS
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
D0
D9
D4
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
DQS
D13
DQS1
DM1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
DQS5
DM5
D1
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS DQS
D10
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
D5
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
DQS
D14
DQS2
DM2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
DQS
DQS6
DM6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
D2
D11
D6
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
DQS
D15
DQS3
DM3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
DQS7
DM7
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
DQS
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
D3
D12
D7
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS DQS
D16
DQS8
DM8
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
D8
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
DQS
*Clock Net Wiring
D3/D0/D5
D4/D1/D6
R=120
Ω
D8/D2/D7
D17/D9/D14
D12/D10/D15
D17
Serial PD
SCL
WP
A0
SA0
A1
SA1
A2
SA2
SDA
* Clock Wiring
Clock
DDR SDRAMs
Input
CK0/CK0
CK1/CK1
CK2/CK2
6 DDR SDRAMs
6 DDR SDRAMs
6 DDR SDRAMs
CK0/1/2
Card
Edge
*D8, D17 is assigned for ECC Comp.
D13/D11/D16
BA0 - BA1
A0 - A12
RAS
CAS
CKE1
CKE0
WE
BA0-BA1: DDR SDRAMs D0 - D17
A0-A12: DDR SDRAMs D0 - D17
RAS: DDR SDRAMs D0 - D17
CAS: DDR SDRAMs D0 - D17
CKE: DDR SDRAMs D9 - D17
CKE: DDR SDRAMs D0 - D8
WE: DDR SDRAMs D0 - D17
VREF
V
SS
V
DDID
V
DDSPD
V
DD
/V
DDQ
SPD
D0 - D17
D0 - D17
D0 - D17
D0 - D17
Strap: see Note 4
Notes:
1. DQ-to-I/O wiring is shown as recom-
mended but may be changed.
2. DQ/DQS/DM/CKE/CS relationships must
be maintained as shown.
3. DQ, DQS, DM/DQS resistors: 22 Ohms +
5%.
4. VDDID strap connections
(for memory device VDD, VDDQ):
STRAP OUT (OPEN): VDD = VDDQ
STRAP IN (VSS): VDD
≠
VDDQ.
5. BAx, Ax, RAS, CAS, WE resistors: 3
Ohms + 5%
V827565K24SA Rev.1.1 March 2008
3
ProMOS TECHNOLOGIES
Pin Configurations (Front Side/Back Side)
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Front
VREF
DQ0
VSS
DQ1
DQS0
DQ2
VDD
DQ3
NC
NC
VSS
DQ8
DQ9
DQS1
VDDQ
CK1
CK1
VSS
DQ10
DQ11
CKE0
VDDQ
DQ16
DQ17
DQS2
VSS
A9
DQ18
A7
VDDQ
DQ19
Pin
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
Front
A5
DQ24
VSS
DQ25
DQS3
A4
VDD
DQ26
DQ27
A2
Vss
A1
CB0*
CB1*
VDD
DQS8*
A0
CB2*
VSS
CB3*
BA1
Key Key
DQ32
VDDQ
DQ33
DQS4
DQ34
VSS
BA0
DQ35
DQ40
Pin
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
Front
VDDQ
WE
DQ41
CAS
VSS
DQS5
DQ42
DQ43
VDD
NC
DQ48
DQ49
VSS
CK2
CK2
VDDQ
DQS6
DQ50
DQ51
VSS
VDDID
DQ56
DQ57
VDD
DQS7
DQ58
DQ59
VSS
NC
SDA
SCL
Pin
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
Back
VSS
DQ4
DQ5
VDDQ
DM0
DQ6
DQ7
VSS
NC
NC
DU
VDDQ
DQ12
DQ13
DM1
VDD
DQ14
DQ15
CKE1
VDDQ
BA2*
DQ20
A12
VSS
DQ21
A11
DM2
VDD
DQ22
A8
DQ23
Pin
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
Back
VSS
A6
DQ28
DQ29
VDDQ
DM3
A3
DQ30
VSS
DQ31
CB4*
CB5*
VDDQ
CK0*
CK0*
VSS
DM8*
A10
CB6*
VDDQ
CB7*
Key key
VSS
DQ36
DQ37
VDD
DM4
DQ38
DQ39
VSS
DQ44
V827565K24SA
Pin
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
Back
RAS
DQ45
VDDQ
CS0
CS1
DM5
VSS
DQ46
DQ47
NC
VDDQ
DQ52
DQ53
NC
VDD
DM6
DQ54
DQ55
VDDQ
NC
DQ60
DQ61
VSS
DM7
DQ62
DQ63
VDDQ
SA0
SA1
SA2
VDDSPD
Pin Names
Pin
CK1, CK1, CK2, CK2
CS0 , CS1
CKE0, CKE1
RAS, CAS, WE
A0 ~ A12
BA0, BA1
DQ0~DQ63
DQS0~DQS7
DM0~DM7
VDD
Pin Description
Differential Clock Inputs
Chip Select Input
Clock Enable Input
Commend Sets Inputs
Address
Bank Address
Data Inputs/Outputs
Data Strobe Inputs/Outputs
Data-in Mask
Power Supply
Pin
VDDQ
VSS
VREF
VDDSPD
SA0~SA2
SCL
SDA
VDDID
DU
NC
Pin Description
DQs Power Supply
Ground
Reference Power Supply
Power Supply for SPD
E
2
PROM Address Inputs
E
2
PROM Clock
E
2
PROM Data I/O
VDD Identification Flag
Do not Use
No Connection
V827565K24SA Rev. 1.1 March 2008
4
ProMOS TECHNOLOGIES
Serial Presence Detect Information
Bin Sort:
D3 (PC3200 @ CL 3-3-3 )
C0 (PC2700 @ CL 2.5-3-3)
V827565K24SA
Function Supported
Byte #
0
Hex Values
D3
80h
Function described
Defines # of Bytes written into serial memory at module man-
ufacturer
Total # of Bytes of SPD memory device
Fundamental memory type
# of row address on this assembly
# of column address on this assembly
# of module Ranks on this assembly
Data width of this assembly
.........Data width of this assembly
VDDQ and interface standard of this assembly
DDR SDRAM cycle time at highest CL
DDR SDRAM Access time from clock at highest CL
DIMM configuration type(Non-parity, Parity, ECC)
Refresh rate & type
Primary DDR SDRAM width
Error checking DDR SDRAM data width
Minimum clock delay for back-to-back random column
address
DDR SDRAM device attributes : Burst lengths supported
DDR SDRAM device attributes : # of banks on each DDR
SDRAM
DDR SDRAM device attributes : CAS Latency supported
D3
128bytes
C0
C0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
256bytes
SDRAM DDR
13
11
2 Ranks
72 bits
-
SSTL
5ns
±0.65ns
6ns
±0.70ns
50h
65h
08h
07h
0Dh
0Bh
02h
48h
00h
04h
60h
70h
02h
82h
08h
08h
01h
Non-parity, ECC
7.8us & Self refresh
x8
x8
t
CCD
=1CLK
2,4,8
4 banks
16
17
0Eh
04h
18
2,2.5 (C0)
2,2.5,3 (D3)
0CLK
1CLK
Differential clock /
non Registered
+/-0.2V voltage tolerance
6.0ns
±0.70ns
7.5ns
±0.75ns
7.5ns
±0.70ns
-
-
60h
70h
75h
75h
0Ch
1Ch
01h
02h
20h
19
20
21
DDR SDRAM device attributes : CS Latency
DDR SDRAM device attributes : WE Latency
DDR SDRAM module attributes
22
23
24
25
26
DDR SDRAM device attributes : General
DDR SDRAM cycle time at 2nd highest CL
DDR SDRAM Access time from clock at 2nd highest CL
DDR SDRAM cycle time at 3rd highest CL
DDR SDRAM Access time from clock at 3rd highest CL
00h
75h
70h
00h
00h
V827565K24SA Rev.1.1 March 2008
5