V826765K24SBIX-C0 datasheet, PDF

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V826765K24SBIX-C0: DescriptionCache DRAM Module, 128MX64, 0.7ns, CMOS, PDMA184; Categorystorage storage; File Size191KB，14 Pages; ManufacturerProMOS Technologies Inc; Environmental Compliance

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V826765K24SBIX-C0 Overview

Cache DRAM Module, 128MX64, 0.7ns, CMOS, PDMA184

V826765K24SBIX-C0 Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Objectid	1126060309
package instruction	DIMM, DIMM184
Reach Compliance Code	compliant
ECCN code	EAR99
Maximum access time	0.7 ns
Maximum clock frequency (fCLK)	166 MHz
I/O type	COMMON
JESD-30 code	R-PDMA-N184
memory density	8589934592 bit
Memory IC Type	CACHE DRAM MODULE
memory width	64
Number of terminals	184
word count	134217728 words
character code	128000000
Maximum operating temperature	70 °C
Minimum operating temperature
organize	128MX64
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	DIMM
Encapsulate equivalent code	DIMM184
Package shape	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	2.5 V
Certification status	Not Qualified
refresh cycle	8192
Maximum standby current	0.16 A
Maximum slew rate	3.28 mA
Nominal supply voltage (Vsup)	2.5 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	NO LEAD
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED

V826765K24SBIX-C0 Preview

V826765K24SB

1GB 184-PIN DDR UNBUFFERED DIMM

128M x 64

Features

■

184 Pin Unbuffered 134,217,728 x 64 bit

Organization DDR SDRAM Modules

■

Utilizes High Performance 64M x 8 DDR

SDRAM in TSOPII packages.

■

Single +2.5V (± 0.2V) Power Supply

■

Single +2.6V (± 0.1V) Power Supply for DDR400

■

Programmable CAS Latency, Burst Length, and

Wrap Sequence (Sequential & Interleave)

■

Auto Refresh (CBR) and Self Refresh

■

All Inputs, Outputs are SSTL-2 Compatible

■

8192 Refresh Cycles every 64 ms

■

Serial Presence Detect (SPD)

■

DDR SDRAM Performance

Description

The V826765K24SB memory module is

organized 134,217,728 x 64 bits in a 184 pin

memory module. The 128M x 64 memory module

uses 16 ProMOS 64M x 8 DDR SDRAM. The x64

modules are ideal for use in high performance

computer systems where increased memory

density and fast access times are required.

Module Speed

Clock Frequency (max.)

Clock Cycle Time CAS Latency = 3

t

CK

t

RCD

t

RP

Clock Cycle Time CAS Latency = 2.5

tRCD parameter

tRP parameter

D3

200

(PC400B)

C0

166

(PC333)

Units

MHz

ns

CLK

5

6

3

-

6

3

V826765K24SB Rev. 1.1 April 2006

1

ProMOS TECHNOLOGIES

Part Number Information

V826765K24SB

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

V

ProMOS

TYPE

8 : DDR

8

2

6 7

6 5

DATA

DEPTH

16 : 16Mb

32 : 32 Mb

64 : 64 Mb

65 : 128 Mb

66 : 256 Mb

K

2

REFRESH

RATE

0: 4K

2: 8K

4

S

B

COMPONENT

REV LEVEL

I

W

PCB TYPE

-

D

3

G : GOLD_LEAD PLATING

W : GOLD_RoHS

L : LOW PROFILE_LEAD PLATING

X : LOW PROFILE_RoHS

VOLTAGE

2 : 2.5V

DATA WIDTH

& COMP DENSITY

65

66

67

68

69

73

74

75

76

77

X64 using 128M

X64 using 256M

X64 using 512M

X64 using 1G

X64 using 2G

X72 using 128M

X72 using 256M

X72 using 512M

X72 using 1G

X72 using 2G

MODULE TYPE

& COMP WIDTH

BANKS

4 : 4 Banks

COMPONENT PKG

LEAD

PLATING

T

S

D

Z

I

J

N

P

GREEN

PACKAGE

DESCRIPTION

TSOP

FBGA

Die-stacked TSOP

Die-stacked FBGA

BASED ON

184PIN DIMM

UNBUFFERED

184PIN DIMM

REGISTERED

200PIN

SO-DIMM

172PIN

Micro-DIMM

X4 X16 X8

I

N

V

J

O

B

K

U

G

M

I/O INTERFACE

S: SSTL_2

SPEED

B0 : PC2100B (133MHz @CL2.5-3-3)

B1 : PC2100A (133MHz @CL2-2-2)

C0 : PC2700 (166MHz @CL2.5-3-3)

D0 : PC3200 (200MHz @CL2.5-3-3)

D3 : PC3200 (200MHz @CL3-3-3)

*RoHS: Restriction of Hazardous Substances

*GREEN: RoHS-compliant and Halogen-Free

V826765K24SB Rev. 1.1 April 2006

2

ProMOS TECHNOLOGIES

Functional Block Diagram

CS1

CS0

DQS0

DM0

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DM

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

CS

DQS

V826765K24SB

DQS4

DM4

DM

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

CS

DQS

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DM

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

CS

DQS

D0

D8

D4

DM

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

CS

DQS

D12

DQS1

DM1

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DM

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

CS

DQS

DQS5

DM5

DM

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

CS DQS

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DM

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

CS

DQS

D1

D9

D5

DM

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

CS

DQS

D13

DQS2

DM2

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DM

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

CS

DQS

DM

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

CS

DQS

DQS6

DM6

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DM

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

CS

DQS

D2

D10

D6

DM

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

CS

DQS

D14

DQS3

DM3

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DM

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

CS

DQS

DQS7

DM7

DM

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

CS

DQS

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DM

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

CS

DQS

D3

D11

D7

DM

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

CS DQS

D15

*Clock Net Wiring

Dram1

Serial PD

SCL

A0

SA0

BA0 - BA1

A0 - A12

RAS

CAS

V

DD

/V

DDQ

A1

SA1

A2

SA2

SDA

Clock Wiring

Clock

SDRAMs

Input

CK0/CK0

CK1/CK1

CK2/CK2

4 SDRAMs

6 SDRAMs

Card

Edge

Dram2

R=120

Ω

Dram3

*(Cap.)

Dram4

*(Cap.)

Dram5

Dram6

BA0-BA1: SDRAMs D0 - D15

A0-A12: SDRAMs D0 - D15

RAS: SDRAMs D0 - D15

CAS: SDRAMs D0 - D15

CKE1

CKE0

WE

CKE: SDRAMs D8 - D15

CKE: SDRAMs D0 - D7

WE: SDRAMs D0 - D15

*If four DRAMs are loaded,

Cap will replace DRAM3,4

0.1uF

D0 - D15

VREF

V

SS

V

DDID

Strap: see Note 4

Notes:

1. DQ-to-I/O wiring is shown as recom-

mended but may be changed.

2. DQ/DQS/DM/CKE/S relationships must

be maintained as shown.

3. DQ, DQS, DM resistors: 22 Ohms.

4. VDDID strap connections

(for memory device VDD, VDDQ):

STRAP OUT (OPEN): VDD = VDDQ

STRAP IN (VSS): VDD

≠VDDQ.

V826765K24SB Rev. 1.1 April 2006

3

ProMOS TECHNOLOGIES

Pin Configurations (Front Side/Back Side)

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

Front

VREF

DQ0

VSS

DQ1

DQS0

DQ2

VDD

DQ3

NC

VSS

DQ8

DQ9

DQS1

VDDQ

CK1

VSS

DQ10

DQ11

CKE0

VDDQ

DQ16

DQ17

DQS2

VSS

A9

DQ18

A7

VDDQ

DQ19

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

Front

A5

DQ24

VSS

DQ25

DQS3

A4

VDD

DQ26

DQ27

A2

Vss

A1

CB0*

CB1*

VDD

DQS8*

A0

CB2*

VSS

CB3*

BA1

Key Key

DQ32

VDDQ

DQ33

DQS4

DQ34

VSS

BA0

DQ35

DQ40

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

Front

VDDQ

WE

DQ41

CAS

VSS

DQS5

DQ42

DQ43

VDD

NC

DQ48

DQ49

VSS

CK2

VDDQ

DQS6

DQ50

DQ51

VSS

VDDID

DQ56

DQ57

VDD

DQS7

DQ58

DQ59

VSS

NC

SDA

SCL

93

94

95

96

97

98

99

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

Back

VSS

DQ4

DQ5

VDDQ

DM0

DQ6

DQ7

VSS

NC

DU

VDDQ

DQ12

DQ13

DM1

VDD

DQ14

DQ15

CKE1

VDDQ

BA2*

DQ20

A12

VSS

DQ21

A11

DM2

VDD

DQ22

A8

DQ23

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

Back

VSS

A6

DQ28

DQ29

VDDQ

DM3

A3

DQ30

VSS

DQ31

CB4*

CB5*

VDDQ

CK0

VSS

DM8*

A10

CB6*

VDDQ

CB7*

Key key

VSS

DQ36

DQ37

VDD

DM4

DQ38

DQ39

VSS

DQ44

V826765K24SB

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

Back

RAS

DQ45

VDDQ

CS0

CS1

DM5

VSS

DQ46

DQ47

NC

VDDQ

DQ52

DQ53

NC

VDD

DM6

DQ54

DQ55

VDDQ

NC

DQ60

DQ61

VSS

DM7

DQ62

DQ63

VDDQ

SA0

SA1

SA2

VDDSPD

Notes:

*

These pins are not used in this module.

Pin Names

CK0~ CK2, CK0~ CK2

CS0, CS1

CKE0, CKE1

RAS, CAS, WE

A0 ~ A12

BA0, BA1

DQ0~DQ63

DQS0~DQS7

DM0~DM7

VDD

Pin Description

Differential Clock Inputs

Chip Select Input

Clock Enable Input

Commend Sets Inputs

Address

Bank Address

Data Inputs/Outputs

Data Strobe Inputs/Outputs

Data-in Mask

Power Supply

VDDQ

VSS

VREF

VDDSPD

SA0~SA2

SCL

SDA

VDDID

DU

NC

Pin Description

DQs Power Supply

Ground

Reference Power Supply

Power Supply for SPD

E

2

PROM Address Inputs

E

2

PROM Clock

E

2

PROM Data I/O

VDD Identification Flag

Do not Use

No Connection

V826765K24SB Rev. 1.1 April 2006

4

ProMOS TECHNOLOGIES

Serial Presence Detect Information

Bin Sort:

D3 (PC3200 @ 3-3-3 )

C0 (PC2700 @ 2.5-3-3)

V826765K24SB

Function Supported

Byte #

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

Hex value

D3

80h

08h

07h

0Dh

0Bh

02h

40h

00h

04h

50h

65h

00h

82h

08h

00h

01h

0Eh

04h

08h

18h

01h

02h

20h

60h

70h

Function described

Defines # of Bytes written into serial memory at module manufacturer

Total # of Bytes of SPD memory device

Fundamental memory type

# of row address on this assembly

# of column address on this assembly

# of module Ranks on this assembly

Data width of this assembly

.........Data width of this assembly

VDDQ and interface standard of this assembly

DDR SDRAM cycle time at highest CAS Latency

DDR SDRAM Access time from clock at highest CL

DIMM configuration type(Non-parity, Parity, ECC)

Refresh rate & type

Primary DDR SDRAM width

Error checking DDR SDRAM data width

Minimum clock delay for back-to-back random column address

DDR SDRAM device attributes : Burst lengths supported

DDR SDRAM device attributes : # of banks on each DDR SDRAM

DDR SDRAM device attributes : CAS Latency supported

D3

128bytes

256bytes

C0

SDRAM DDR

13

11

2 Ranks

64 bits

-

SSTL 2.5V

5ns

±0.65ns

6ns

±0.70ns

Non-parity, Non-ECC

7.8us & Self refresh

x8

N/A

t

CCD

=1CLK

2,4,8

4 banks

2.5(C0)

2.5, 3(D3)

0CLK

1CLK

Differential clock /

non Registered

+/-0.2V voltage tolerance

Concurrent Auto Precharge

tRAS Lock Out

6.0ns

±0.70ns

-

15ns

-

18ns

60h

70h

00h

3Ch

19

20

21

DDR SDRAM device attributes : CS Latency

DDR SDRAM device attributes : WE Latency

DDR SDRAM module attributes

22

DDR SDRAM device attributes : General

C0h

23

24

25

26

27

DDR SDRAM cycle time at second highest CL

DDR SDRAM Access time from clock at second highest CL

DDR SDRAM cycle time at third highest CL

DDR SDRAM Access time from clock at third highest CL

Minimum row precharge time (=t

RP

)

00h

48h

V826765K24SB Rev. 1.1 April 2006

5

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Description	Cache DRAM Module, 128MX64, 0.7ns, CMOS, PDMA184	DDR DRAM Module, 128MX64, 0.7ns, CMOS, GREEN, DIMM-184	DDR DRAM Module, 128MX64, 0.7ns, CMOS, GREEN, DIMM-184	Cache DRAM Module, 128MX64, 0.65ns, CMOS, PDMA184	Cache DRAM Module, 128MX64, 0.65ns, CMOS, PDMA184	Cache DRAM Module, 128MX64, 0.65ns, CMOS, PDMA184
Is it Rohs certified?	conform to	conform to	conform to	incompatible	conform to	incompatible
package instruction	DIMM, DIMM184	DIMM, DIMM184	DIMM, DIMM184	DIMM, DIMM184	DIMM, DIMM184	DIMM, DIMM184
Reach Compliance Code	compliant	compliant	compliant	compliant	compliant	compliant
ECCN code	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99
Maximum access time	0.7 ns	0.7 ns	0.7 ns	0.65 ns	0.65 ns	0.65 ns
Maximum clock frequency (fCLK)	166 MHz	200 MHz	166 MHz	200 MHz	200 MHz	200 MHz
I/O type	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON
JESD-30 code	R-PDMA-N184	R-XDMA-N184	R-XDMA-N184	R-PDMA-N184	R-PDMA-N184	R-PDMA-N184
memory density	8589934592 bit	8589934592 bit	8589934592 bit	8589934592 bit	8589934592 bit	8589934592 bit
Memory IC Type	CACHE DRAM MODULE	DDR DRAM MODULE	DDR DRAM MODULE	CACHE DRAM MODULE	CACHE DRAM MODULE	CACHE DRAM MODULE
memory width	64	64	64	64	64	64
Number of terminals	184	184	184	184	184	184
word count	134217728 words	134217728 words	134217728 words	134217728 words	134217728 words	134217728 words
character code	128000000	128000000	128000000	128000000	128000000	128000000
Maximum operating temperature	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C
organize	128MX64	128MX64	128MX64	128MX64	128MX64	128MX64
Output characteristics	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
Package body material	PLASTIC/EPOXY	UNSPECIFIED	UNSPECIFIED	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	DIMM	DIMM	DIMM	DIMM	DIMM	DIMM
Encapsulate equivalent code	DIMM184	DIMM184	DIMM184	DIMM184	DIMM184	DIMM184
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
power supply	2.5 V	2.6 V	2.5 V	2.6 V	2.6 V	2.6 V
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
refresh cycle	8192	8192	8192	8192	8192	8192
Maximum standby current	0.16 A	0.16 A	0.16 A	0.16 A	0.16 A	0.16 A
Maximum slew rate	3.28 mA	3.36 mA	3.28 mA	3.36 mA	3.36 mA	3.36 mA
Nominal supply voltage (Vsup)	2.5 V	2.6 V	2.5 V	2.6 V	2.6 V	2.6 V
surface mount	NO	NO	NO	NO	NO	NO
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal form	NO LEAD	NO LEAD	NO LEAD	NO LEAD	NO LEAD	NO LEAD
Terminal pitch	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
Is it lead-free?	Lead free	-	-	Contains lead	Lead free	Contains lead

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