PO74HSTL85353A
www.potatosemi.com
LVCMOS and XTAL Input to HSTLOutput 1:4 Fanout Buffer
300MHz HSTL Potato Chip
FEATURES:
. Patented Technology
. Four HSTL differential outputs
. Two single LVTTL/LVCMOS inputs
(selectable LVCMOS/ LVTTL clock or crystal input)
. Operating frequency up to 300MHz with 15pf load
. Very low output pin to pin skew < 50ps
. 3.4-ns propagation delay (max)
. 2.4V to 3.6V power supply
. Industrial temperature range: –40°C to 85°C
. 20-pin TSSOP package
DESCRIPTION:
The PO74HSTL85353A is a low-skew, 1-to-4 differential
fanout buffer targeted to meet the requirements of
high-performance clock and data distribution applications.
The device is implemented on CMOS technology and has
a fully differential internal architecture that is optimized to
achieve low signal skews at operating frequencies of up to
300MHz .
The device features two inputs, one is LVTTL / LVCMO
signal and the other is crystal input. This mux is
controlled by the CLK_SEL pin. The PO74HSTL85353A
functions as a signal-level translator and fanout on
LVCMOS / LVTTL single-ended signal to four HSTL
differential loads. Since the PO74HSTL85353A
introduces negligible jitter to the timing budget, it is the
ideal choice for distributing high frequency, high precision
clocks across back-planes and boards in communication
systems.
Pin Configuration
V
EE
CLK_EN
CLK_SEL
CLK
nc
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Logic Block Diagram
Q0
nQ0
V
CC
Q1
nQ1
Q2
nQ2
V
CC
Q3
nQ3
CLK_EN
Pullup
D
LE
Q
CLK
Pulldown
XTAL_IN
XTAL_OUT
CLK_SEL
Pulldown
0
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
XTAL_IN
XTAL_OUT
nc
nc
V
CC
OSC
1
Potato Semiconductor Corporation
1
01/01/10
PO74HSTL85353A
www.potatosemi.com
LVCMOS and XTAL Input to HSTLOutput 1:4 Fanout Buffer
300MHz HSTL Potato Chip
Pin Definitions
Pin
10,13,18
5, 8, 9
3
4
6, 7
2
1
19, 16,14,11
20, 17,15,12
VCC
NC
CLK_SEL
CLK0
XTAL_IN XTAL_OUT
Name
I/O
VCC
I,PD
I,PD
I
I,PU
GND
O
O
Type
Power
LVCMOS
No connect
Description
Power supply, positive connection
Input clock select with pull down resistor
LVCMOS/ LVTTL
LVCOMS / LVTTL clock input
LVCMOS/ LVTTL
crystal oscillator interface
LVCMOS/ LVTTL
Clock enabled
CLK_EN
VEE
Q[0:3]#
Q[0:3]
Power
HSTL
HSTL
Power Ground
Complement output
Ture output
Control Input Function Table
CLK_EN
0
0
1
1
CLK_SEL
0
0
1
Inputs
Selected Source
CLK
CLK
Q0:Q3
Disabled; LOW
Enabled
Outputs
nQ0:nQ3
Disabled; HIGH
Disabled; HIGH
Enabled
Enabled
XTAL_IN, XTAL_OUT
XTAL_IN, XTAL_OUT
Disabled; LOW
Enabled
1
Input/ Output Function Table
Inputs
CLK
0
1
Q0:Q3
LOW
HIGH
Outputs
nQ0:nQ3
HIGH
LOW
Pin Characteristics
R
PULLUP
C
IN
Symbol
Input Capacitance
Parameter
Test Conditions
Minimum
Typical
88
88
4
Maximum
Units
K
K
pF
Input Pullup Resistor
R
PULLDOWN
Input Pulldown Resistor
Potato Semiconductor Corporation
2
01/01/10
PO74HSTL85353A
www.potatosemi.com
LVCMOS and XTAL Input to HSTLOutput 1:4 Fanout Buffer
300MHz HSTL Potato Chip
Maximum Ratings
Description
Storage Temperature
Operation Temperature
Operation Voltage
Input Voltage
Output Voltage
Max
-65 to 150
-40 to 85
-0.5 to +4.6
-0.5 to +5.5
-0.5 to Vcc+0.5
Unit
°C
°C
V
V
V
Note:
stresses greater than listed under
Maximum
Ratings
may
cause
permanent damage to the device. This
is a stress rating only and functional
operation of the device at these or any
other conditions above those indicated
in the operational sections of this
specification is not implied. Exposure
to absolute maximum rating conditions
for extended periods may affect
reliability specification is not implied.
DC Electrical Characteristics
Symbol
Description
Output High voltage
Output Low voltage
Clamp diode voltage
Test Conditions
Vcc=3V Vin=V
IH
or V
IL
, I
OH
= -12mA
Vcc=3V Vin=V
IH
or V
IL
, I
OH
=12mA
Vcc = Min. And
I
IN
= -18mA
Min
Typ
Max
Unit
V
OH
V
OL
V
IK
2.4
-
-
3
0.3
-0.7
-
0.5
-1.2
V
V
V
Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
Notes:
1.
2.
3.
4.
5.
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at Vcc = 3.3V, 25
°C
ambient.
This parameter is guaranteed but not tested.
Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
VoH = Vcc – 0.6V at rated current
Potato Semiconductor Corporation
3
01/01/10
PO74HSTL85353A
www.potatosemi.com
LVCMOS and XTAL Input to HSTLOutput 1:4 Fanout Buffer
300MHz HSTL Potato Chip
Power Supply Characteristics
Symbol
Description
Quiescent Power Supply Current
Test Conditions (1)
Vcc=Max, Vin=Vcc or GND
Min
Typ
Max
Unit
Icc
Q
Notes:
1.
2.
3.
4.
-
0.1
30
uA
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at Vcc = 3.3V, 25°C ambient.
This parameter is guaranteed but not tested.
Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
Crystal Oscillator Test Conditions
Te s t C o n d it io n s
Output Frequency
3.579
14.318
28
50
250
Un its
X1=3.579MHz, C4=100pf, C5=100pf
X1=14.318MHz, C4=50pf, C5=50pf
X1=28MHz, C4=50pf, C5=50pf, R1=5.1K
X1=50MHz, C4=50pf, C5=50pf, R1=3K
X1=250MHz, C4=0, C5=0, R1=1K
See schematic example.
MHz
MHz
MHz
MHz
MHz
Notes:
Switching Characteristics
Symbol
Description
Propagation Delay CLKA or CLKB to Output pair
Test Conditions (1)
CL = 15pF
0.8V – 2.0V
CL = 15pF, 125MHz
CL = 15pF, 125MHz
CL =15pF
M ax
Unit
t
PD
tr/tf
tsk(o)
tsk(pp)
fmax
Notes:
3.4
0.8
50
350
300
250
ns
ns
ps
ps
MHz
Rise/Fall Time
Output Pin to Pin Skew (Same Package)
Output Skew (Different Package)
Input Frequency
1. See test circuits and waveforms.
2. tpLH, tpHL, tsk(p), and tsk(o) are production tested. All other parameters guaranteed but not production tested.
3. Airflow of 1m/s is recommended for frequencies above 133MHz
Potato Semiconductor Corporation
4
01/01/10
PO74HSTL85353A
www.potatosemi.com
LVCMOS and XTAL Input to HSTLOutput 1:4 Fanout Buffer
300MHz HSTL Potato Chip
Test Waveforms
FIGURE 1.
LVTTL/LVCMOS INPUT WAVEFORM DEFINITION
3V
Input
FIGURE 2.
HSTL OUTPUT
1.5V
0V
tr,tf,
20-80%
VO
FIGURE 3.
Propogation Delay, Output pulse skew, and output-to-output skew for D to output pair
INPUT
CLOCK
TPLH
TPD
OUTPUT
CLOCK
TPHL
VO
tSK(O)
ANOTHER
OUTPUT
CLOCK
FIGURE 4.
CLK_EN Timing Diagram
Disabled
Enabled
CLK
CLK_EN
nQ0:nQ3
Q0:Q3
Potato Semiconductor Corporation
5
01/01/10
京公网安备 11010802033920号
EEWORLD
