SiW3000
0
Features
• Single-chip IC with 2.4 GHz
transceiver, baseband processor,
and on-chip protocol stack for
Bluetooth® wireless technology
• Compliant with Bluetooth
specification 1.2 features.
• Low cost 0.18 µm CMOS process
technology.
• 1.8 V analog and digital core
voltages; 1.62 V to 3.63 V external
I/O interface voltage.
• Typical -85 dBm receiver sensitivity,
+2 dBm transmitter power for up to
100 meters nominal range.
• On-chip VCO and PLL support
multiple GSM/GPRS and CDMA
cellular reference clock frequencies.
• Hardware AGC dynamically adjusts
receiver performance in changing
environments.
• Integrated 32-bit ARMTDMI®
processor for extended features.
• Full piconet connectivity with support
for up to 7 active and 8 parked
slaves.
• Scatternet compatible with
Microsoft® HID devices.
• Supports three SCO voice channels.
• Channel Quality Driven Data Rate
(CQDDR) controls multi-slot packets
to minimize packet overhead and
maximize data throughput.
• Option for Bluetooth + Wi-Fi
coexistence.
ULTIMATEBLUE™
RADIO PROCESSOR
Sleep Control
2.4 GHz
Direct
Conversion
Transceiver
Power
Management
ARM7TDMI®
Processor
SRAM
Data
ROM
HCI
Firmware
Up to 2 Mbs
USB Full
Speed
MODEM
Internal
32 kHz
Clock
UART
USB
GPIO
Audio
CODEC
Interface
To Antenna
Bluetooth
Baseband
with CVSD
System I/O
CODEC
Master or
Slave
Product Description
The SiW3000 UltimateBlue™ Radio Processor is a recent innovation for
Bluetooth® wireless technology. It combines the industry's best performing
and most highly integrated radio design with an ARMTDMI® processor
using CMOS technology. The SiW3000 uses direct conversion (zero-IF)
architecture. This allows digital filtering for excellent interference rejection as
compared to low IF solutions and also results in fewer spurious responses.
The lower-layer protocol stack software is integrated into the on-chip ROM.
Optional external Flash memory is also supported. The SiW3000 is
compliant with Bluetooth specification 1.2 features.
The device is available in multiple packages and bare die form with a
guaranteed operating temperature range from -40°C to +85°C and an
extended high temperature range to +105°C.
2.3 ~ 3.63 V
Voltage
Reg
Fast
Locking
PLL
Crystal or Reference Clock
Block Diagram
Applications
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Mobile phones.
Notebook and desktop PCs.
Cordless headsets.
Personal digital assistants (PDAs).
Computer accessories, peripherals,
and wireless printers/
keyboards/mice).
Ordering Information
SiW3000
UltimateBlue™ Radio Processor
Optimum Technology Matching® Applied
Si BJT
Si Bi-CMOS
GaInP/HBT
GaAs HBT
SiGe HBT
GaN HEMT
GaAs MESFET
Si CMOS
SiGe Bi-CMOS
RF Micro Devices, Inc.
7628 Thorndike Road
Greensboro, NC 27409, USA
Tel (336) 664 1233
Fax (336) 664 0454
http://www.rfmd.com
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SiW3000
Radio Features
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Direct-conversion architecture with no external IF filter or VCO resonator components.
Single ended RF I/O reduces system bill of materials (BOM) costs by eliminating the need to use external balun and
switch circuits.
On-chip VCO and PLL support multiple GSM, CDMA, GPRS standard reference clock frequencies.
Low out-of-band spurious emission transmitter prevents blocking of sensitive mobile phone RF circuits.
No tuning during production.
Internal temperature compensation circuit stabilizes performance across wide operating temperature.
Fast settling synthesizer reduces power consumption.
Up to 100 meter operating range in standard configuration without using an external PA.
ARM7TDMI processor core running at 16 MHz.
Digital GFSK modem for maximum performance and lower packet error rate.
On-chip CVSD conversion with hardware based gain adjustments to enhance audio quality.
Sleep control interface for low power operation modes.
Software execution from ROM or external FLASH memory.
Full piconet connectivity with support for up to 7 active and 8 parked slaves.
Able to establish up to 3 SCO connections.
Scatternet capable and compatible with Microsoft HID devices.
Standard Bluetooth test modes.
Low power connection states supported with hold, sniff, and park modes.
Channel Quality Driven Data Rate (CQDDR) optimizes data transfer rate in noisy or weak signal environments
Audio (SCO) routing over HCI interface for VOIP applications.
Support for Bluetooth + Wi-Fi coexistence technology.
Verified compatibility with multiple upper-layer stack vendors.
Extensive vendor specific HCI commands enables hardware specific controls.
Optional upper-layer stack and profiles can be licensed and integrated into the IC.
Adaptive frequency hopping (AFH).
Faster connections.
LMP improvements.
Baseband Features
Standard Protocol Stack Features
Additional Protocol Stack Features
Bluetooth 1.2 Features
External System Interfaces
Host HCI Transport (H:2 USB)
The USB device interface provides a physical transport between the SiW3000 and the host for the transfer of Bluetooth
control signals and data. This transport layer is fully compliant with Section H:2 of the Bluetooth specification with all end
points supported. The SiW3000 USB interface encompasses three I/O signals: USB_DPLS, USB_DMNS, and
USB_DPLS_PULLUP. If the USB transport is not used, the USB_DPLS and USB_DMNS pins should be grounded to
reduce current consumption.
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60 0049 R01Drf SiW3000 Radio Processor DS
SiW3000
Host HCI Transport (H:4 UART)
The high speed UART interface provides the physical transport between the SiW3000 and the application host for the
transfer of Bluetooth control signals and data compliant to Section H:4 of the Bluetooth specification. The table below
shows the supported baud rates. The default baud rate is 115,200, but can be configured depending on the application.
SiW3000 Radio Processor HCI UART Parameters
Number of data bits
Parity bit
Stop bit
Flow control
Host flow-off response requirement from the SiW3000
SiW3000 IC flow-off response requirement from host
Supported baud rates
a.Default baud rate.
8
No parity
1 stop bit
RTS/CTS
8 bytes
2 bytes
9.6k, 19.2k, 38.4k, 57.6k, 115.2k
a
, 230.4k, 460.8k, 500k, 921.6k,
1M, 1.5M, 2M
Required Host Setting
Host HCI Transport (H:5 3-Wire UART)
To reduce the number of signals and increase reliability of the HCI UART interface, a 3-wire UART using either the
Bluetooth H:5 or BCSP protocol is supported. The selection between H:4, H:5, and BCSP is done automatically by the
SiW3000, or can be set in NVM.
SiW3000 Radio Processor HCI 3-Wire UART Parameters
Number of data bits
Parity bit
Stop bit
Error detection
Sleep modes
Required Host Setting
8
Even
1 stop bit
Slip and checksum
Shallow and deep
Audio CODEC Interface
The SiW3000 supports direct interface to an external audio CODEC or PCM host device. The interface is easily config-
ured to support:
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Standard 64-kHz PCM clock rate.
Up to 2-MHz clock rates with support for multi-slot handshakes and synchronization.
Either master or slave (Motorola SSI) mode.
Configuration of the CODEC interface is done by the firmware during boot-up by reading non-volatile memory (NVM)
parameters. The following are examples of supported CODEC modes:
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Generic 64-kHz audio CODEC (e.g., OKI MSM-7702).
Motorola MC145481 or similar CODEC as master.
QUALCOMM MSM chip set audio port.
GSM/GPRS baseband IC audio ports.
Programmable I/O (PIO)
Up to twenty-nine (29) programmable IO (PIO) ports are available for customer use in the SiW3000. Three of these PIOs
are dedicated and the remaining PIOs are shared with other functions. Availability of PIOs will depend on system config-
uration. The table below identifies the all twenty-nine PIOs and their usage. The PIO ports can be set to input or output.
Reading, writing, and controlling the PIO pins by the host application software can be done via vendor specific HCI com-
mands.
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SiW3000
PIO#
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Shared I/O
None
None
None
D[8]
D[4]
D[5]
D[6]
D[7]
PWR_REG_EN
D[15]
WE_N
A[16]
A[17]
A[11]
USB_DPLS_PULLUP
Sampled at Reset
Yes
Yes
Yes
No
No
No
No
No
No
No
No
No
No
No
No
PIO#
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Shared I/O
PCM_OUT
PCM_IN
PCM_CLK
PCM_SYNC
EXT_WAKE
HOST_WAKEUP
UART_RXD
UART_TXD
UART_CTS
UART_RTS
A[18]
TX_RX_SWITCH
D[9]
D[10]
Sampled at Reset
No
No
No
No
No
No
No
No
No
No
No
No
No
No
External Memory Interface
The Ultimate 3000 Radio Processor is a true single chip device and does not require additional memory for standard
below HCI protocol functions. An external memory interface is available for adding optional memory. If external Flash
memory will be used, the read access time of the device must be 100 ns or less.
The external memory interface permits connection to Flash and SRAM devices. The interface has an 18-bit address bus
and a 16-bit data bus for a total addressable memory of 512 KB. In certain embedded applications, both SRAM and
Flash can be installed by using the high order address bit as an alternate chip select.
Signal
Address A[1] - A[18]
Data D[0] - D[15]
FCS_N
OE_N
WE_N
Description
18-bit address bus
16-bit data bus
Chip select
Output enable
Write enable
External EEPROM Controller and Interface
This interface is intended for use with ROM-based solutions. The EEPROM is not required for configurations with exter-
nal flash. The EEPROM is the non-volatile memory (NVM) in the system and contains the system configuration parame-
ters such as the Bluetooth device address, the CODEC type, as well as other parameters. These default parameters are
set at the factory, and some parameters will change depending on the system configuration. Optionally, the non-volatile
memory parameters can be downloaded from the host processor at boot up eliminating the need for EEPROM. Please
consult the application support team for details. The EEPROMs should have a serial I
2
C interface with a minimum size of
2 Kbits and 16-byte page write buffer capabilities.
Power Management
The HOST_WAKEUP and EXT_WAKE signals are used for power management. HOST_WAKEUP is an output signal
used to wake up the host. EXT_WAKE is an input signal used by the host to wake up the SiW3000 Radio Processor from
sleep mode. For more information on the usage of HOST_WAKE and EXT_WAKE, please refer to RFMD application
note 62 0031.
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60 0049 R01Drf SiW3000 Radio Processor DS
SiW3000
General System Requirements
System Reference Clock
The SiW3000 chip can use either an external crystal or a reference clock as the system clock input. The supported fre-
quencies are: 9.6 MHz, 12 MHz, 12.8 MHz, 13 MHz, 14.4 MHz, 15.36 MHz, 16 MHz, 16.8 MHz, 19.2 MHz, 19.68 MHz,
19.8 MHz, 26 MHz, 32 MHz, 38.4 MHz, and 48 MHz. The default reference frequency can be selected by setting the
proper system configuration parameter in the non-volatile memory (NVM). If the USB HCI transport will be used, the ref-
erence clock must be 32 MHz.
The system reference crystal/clock must have accuracy of ±20 PPM or better to meet the specification of Bluetooth. To
facilitate design and production, the SiW3000 processor incorporates internal crystal calibration circuits to allow factory
calibration of initial crystal frequency accuracy.
Low Power Clock
For the Bluetooth low power clock, a 32.768-kHz crystal may be used to drive the SiW3000 oscillator circuit, or alterna-
tively, a 32.768-kHz reference clock signal can be used instead of a crystal. If the lowest power consumption is not
required during low-power modes such as sniff, hold, park, and idle modes, the 32.768-kHz crystal may be omitted in the
design. If the 32.768-kHz clock source will be used, the clock source should be connected to the CLK32_IN pin and must
meet the following requirements:
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•
For AC-coupled via 100 pF or greater (peak-to-peak voltage):
400 mV
P-P
< CLK32_IN < V
DD_C
For DC-coupled:
CLK32_IN minimum peak voltage < VIL
CLK32_IN maximum peak voltage > VIH
Where V
IL
= 0.3 * V
DD_C
Where V
IH
= 0.7 * V
DD_C
For both cases, the signal is not to exceed:
-0.3 V < CLK32_IN < V
DD_C
+ 0.3 V
Also, the CLK32_OUT pin must be coupled to V
DD_P
or GND through a 100 nF capacitor.
Power Supply Description
The SiW3000 Radio Processor operates at 1.8 V core voltage for internal analog and digital circuits. The chip has inter-
nal analog and digital voltage regulators simplifying power supply requirements to the chip. The internal voltage regula-
tors can be supplied directly from a battery or from other system voltage sources. Optionally, the internal regulators can
be by-passed if 1.8 V regulated source is available on the system.
Function
Regulator input pin
Regulator output pin
Internal Analog Regulator
V
BATT_ANA
= 2.3 to 3.63 V
V
CC_OUT
= 1.8 V
Internal Digital Regulator
V
BATT_DIG
= 2.3 to 3.63 V
V
DD_C
= 1.8 V
Table 1. Internal Regulator Used
Function
Circuit voltage supply pin
Analog Core Circuits
V
CC
= 1.8 V
Digital Core Circuits
V
DD_C
= 1.8 V
Table 2. Internal Regulator Bypassed
Note: Both regulators can be bypassed if external regulation is desired. When bypassing the analog regulator, the VBATT_ANA and VCC_OUT pins
must be tied together and the external analog voltage (1.8 V) should be applied to the VBATT_ANA pin. When bypassing the digital regulator, the
VBATT_DIG pin should be left unconnected and the external digital voltage (1.8 V) should be applied to VBB_OUT pin.
The power for the I/Os is taken from a separate source (V
DD_P
). V
DD_P
can range from 1.62 to 3.63 Volts to maintain
compatibility with a wide range of peripheral devices. Please check the pin list for the exact pins that are powered from
the V
DD_P
source. Power for the USB circuits is taken from a separate source (V
DD_USB
).
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