2.4GHz DSSS Micro Radio Module with Integrated Antenna
AW24MxxL
Data Sheet
1
Features
3
Applications
The AW24MxxL is a 2.4-GHz Direct Sequence Spread Spectrum
(DSSS) complete radio module which includes the Cypress radio
integrated circuit CyFi™ CYRF7936, integrated Antenna, and all
external components
Operates in the unlicensed worldwide Industrial, Scientific and
Medical (ISM) band (2.400 GHz–2.483 GHz)
21mA operating current (Transmit @ –5 dBm)
Transmit power up to +4 dBm
Receive sensitivity up to –97 dBm
Sleep Current <1
µA
Operating range of up to 20m indoor or 40m LOS.
DSSS data rates up to 250 kbps, GFSK data rate of 1 Mbps
Auto Transaction Sequencer (ATS) - no micro controller
intervention
Framing, Length, CRC16, and Auto ACK
Fast Startup and Fast Channel Changes
Separate 16-byte Transmit and Receive FIFOs
AutoRate™ - dynamic data rate reception
Receive Signal Strength Indication (RSSI)
4-MHz SPI microcontroller interface
No proprietary software required
Serial Peripheral Interface (SPI) control while in sleep mode
Vertical or horizontal mounting
Operating voltage from 2.4 to 3.6 volts
Operating temperature from -20°C to 70°C
Size: 16 mm x 13.5 mm (~0.6” x 0.5”)
Weight: 2 grams
FCC Modular Approval Grant to meet FCC Part 15, EN 300 328-
1, EN 301 489-1, EN 301 489-7 and Industry Canada RSS-210
standards In Progress.
An FCC Module Approval (MA) Grant provides customers
significant cost savings, by allowing customers to adopt the
AW24MXXL FCC ID into their own products
2
Functional Description
The Artaflex AW24MXXL Wireless Radio Module offers a
complete radio module solution for integration into existing or
new 2.4-GHz products.
The AW24MXXL is tested for functional operation and is
FCC/ETSI (EU)/Industry Canada certified. The module is
supplied with integrated or external antenna options.
The AW24MxxL is available in a small PCB design and can be
mounted horizontally or vertically to the device PCB via a 12-
pin header. The pin-out of the header is shown in the
Connector Footprint section.
PC Human Interface Devices (HID)
Wireless Keyboards and Mice
VOIP and Wireless Headsets
Wireless Gamepads
Remote Control
White Goods (Smart Appliances)
Window unit air conditioners
Kitchen compactors
Dishwashers
Washers
Dryers
Consumer
Sports and Leisure Equipment
Remote Controls
Audio Subwoofer
Presenter Tools
Locator Alarms
Toys
Building/Home Automation
Automatic Meter Readers (AMR)
On-Site Paging Systems
Garage door opener
Alarm and Security
Lighting Control
Climate Control
Fan Control
Industrial Control
Active RFID and asset tracking systems
Inventory Management
Point-of-sale systems
Factory Automation
Data Acquisition
Transportation
Remote Keyless Entry with acknowledgement (RKE)
Airline Baggage Tracking
Diagnostics
Artaflex Inc.
215 Konrad Crescent
Markham, Ontario, Canada
L3R8T9
905-479-0148
DS-102-0006-R1.5
Revised 04 Jan 2013
Page 1 of 13
http://www.artaflexmodules.com
2.4GHz DSSS SPI Radio with Integrated Antenna
AW24MxxL
Data Sheet
*Figure 1 – Module Schematic (Header version)
*Figure 2– Module Schematic (SMT Version)
Artaflex Inc.
215 Konrad Crescent
Markham, Ontario, Canada
L3R8T9
905-479-0148
DS-102-0006-R1.5
Revised 04 Jan 2013
Page 2 of 13
http://www.artaflexmodules.com
2.4GHz DSSS SPI Radio with Integrated Antenna
AW24MxxL
Data Sheet
3.1
Reference Documentation
TM
For information on technical details of the Cypress Semiconductor, CYRF7936 CyFi , 2.4-GHz DSSS Radio system on chip such
as register settings, timing, application interfaces, and clocking, refer to the device data sheet CYFI7936 available on the Cypress
Web Site at:-
www.cypress.com
•
The following is the link , known at the time of publication that accompany this data sheet:
http://download.cypress.com.edgesuite.net/design_resources/datasheets/contents/cyrf7936_8.pdf?key=1229340511568
Artaflex Inc.
215 Konrad Crescent
Markham, Ontario, Canada
L3R8T9
905-479-0148
DS-102-0006-R1.5
Revised 04 Jan 2013
Page 3 of 13
http://www.artaflexmodules.com
2.4GHz DSSS SPI Radio with Integrated Antenna
AW24MxxL
Data Sheet
4
Functional Overview
The AW24MXXL Module provides a complete SPI to RF antenna wireless MODEM. The module is designed to implement wireless
device links operating in the worldwide 2.4-GHz ISM frequency band. It is intended for systems compliant with world-wide
regulations covered by Europe ETSI EN 301 489-1, ETSI EN 301 489-7, & ETSI EN 300 328-1, USA FCC Part 15 and Industry
Canada RSS-210 standards.
The module contains a 2.4-GHz 1-Mbps GFSK radio transceiver, packet data buffering, packet framer, DSSS baseband controller,
Received Signal Strength Indication (RSSI), and SPI interface for data transfer and device configuration.
The radio supports 80 discrete 1-MHz channels (regulations may limit the use of some of these channels in certain jurisdictions). In
DSSS modes the baseband performs DSSS spreading/de-spreading, while in GFSK Mode (1 Mb/s - GFSK) the baseband
performs Start of Frame (SOF), End of Frame (EOF) detection and CRC16 generation and checking. The baseband may also be
configured to automatically transmit Acknowledge (ACK) handshake packets whenever a valid packet is received.
When in receive mode, with packet framing enabled, the device is always ready to receive data transmitted at any of the supported
bit rates, except SDR, enabling the implementation of mixed-rate systems in which different devices use different data rates. This
also enables the implementation of dynamic data rate systems, which use high data rates at shorter distances and/or in a low-
moderate interference environment, and change to lower data rates at longer distances and/or in high interference environments.
4.1
Link Layer Modes
The AW24MXXL module supports the following data packet framing features:
SOP
– Packets begin with a 2-symbol Start of Packet (SOP) marker. This is required in GFSK and 8DR modes, but is optional in
DDR mode and is not supported in SDR mode; if framing is disabled then an SOP event is inferred whenever two successive
correlations are detected. The SOP_CODE_ADR code used for the SOP is different from that used for the “body” of the packet and
if desired may be a different length. SOP must be configured to be the same length on both sides of the link.
EOP
– There are two options for detecting the end of a packet. If SOP is enabled, then a packet length field may be enabled.
GFSK and 8DR must enable the length field. This is the first 8-bits after the SOP symbol, and is transmitted at the payload data
rate. If the length field is enabled, an End of Packet (EOP) condition is inferred after reception of the number of bytes defined in the
length field, plus two bytes for the CRC16 (if enabled—see below). The alternative to using the length field is to infer an EOP
condition from a configurable number of successive non-correlations; this option is not available in GFSK mode and is only
recommended to enable when using SDR mode.
CRC16
– The device may be configured to append a 16-bit CRC16 to each packet. The CRC16 uses the USB CRC polynomial
with the added programmability of the seed. If enabled, the receiver will verify the calculated CRC16 for the payload data against
the received value in the CRC16 field. The starting value for the CRC16 calculation is configurable, and the CRC16 transmitted
may be calculated using either the loaded seed value or a zero seed; the received data CRC16 will be checked against both the
configured and zero CRC16 seeds.
CRC16 detects the following errors:
Any one bit in error
Any two bits in error (no matter how far apart, which column, and so on)
Any odd number of bits in error (no matter where they are)
An error burst as wide as the checksum itself
4.2
Packet Buffers
All data transmission and reception utilizes the 16-byte packet buffers—one for transmission and one for reception.
The transmit buffer allows a complete packet of up to 16-bytes of payload data to be loaded in one burst SPI transaction, and then
transmitted with no further micro controller intervention. Similarly, the receive buffer allows an entire packet of payload data up to
16 bytes to be received with no firmware intervention required until packet reception is complete.
The AW24MXXL module supports packet length of up to 40 bytes; interrupts are provided to allow a micro controller to use the
transmit and receive buffers as FIFOs. When transmitting a packet longer than 16 bytes, the micro controller can load 16-bytes
initially, and add further bytes to the transmit buffer as transmission of data creates space in the buffer. Similarly, when receiving
packets longer than 16 bytes, the micro controller must fetch received data from the FIFO periodically during packet reception to
prevent it from overflowing.
Artaflex Inc.
215 Konrad Crescent
Markham, Ontario, Canada
L3R8T9
905-479-0148
DS-102-0006-R1.5
Revised 04 Jan 2013
Page 4 of 13
http://www.artaflexmodules.com
2.4GHz DSSS SPI Radio with Integrated Antenna
AW24MxxL
Data Sheet
4.3
Auto Transaction Sequencer (ATS)
The AW24MXXL module provides automated support for transmission and reception of acknowledged data packets.
When transmitting a data packet, the device automatically starts the crystal and synthesizer, enters transmit mode, transmits the
packet in the transmit buffer, and then automatically switches to receive mode and waits for a handshake packet and then
automatically reverts to sleep mode or idle mode when either an ACK packet is received, or a timeout period expires.
Similarly, when receiving in transaction mode, the device waits in receive mode for a valid packet to be received, and then
automatically transitions to transmit mode, transmits an ACK packet, and then switches back to receive mode to await the next
packet. The contents of the packet buffers are not affected by the transmission or reception of ACK packets.
In each case, the entire packet transaction takes place without any need for micro controller firmware action; to transmit data the
micro controller simply needs to load the data packet to be transmitted, set the length, and set the TX GO bit. Similarly, when
receiving packets in transaction mode, firmware simply needs to retrieve the fully received packet in response to an interrupt
request indicating reception of a packet.
4.4
Data Rates
By combining the DATA_CODE_ADR code lengths and data transmission modes described above, the AW24MXXL supports the
following modes and data rates.
Table 1 - Data Rates
RF Transmission Mode
GFSK
32-Chip 8DR
[2]
64-chip 8DR
[3]
32-chip DDR
[3]
64-chip DDR
[2,3]
64-chip SDR
Raw Data Rate kbps
1,000.00
250.00
125.00
62.50
31.25
15.63
5
SPI Communication
The AW24MXXL has an SPI interface supporting communications between an application MCU and one or more slave
devices (including the AW24MXXL). The SPI interface supports single-byte and multi-byte serial transfers using either 4-pin
or 3-pin interfacing. The SPI communications interface consists of Slave Select (
)
, Serial Clock (SCK), and Master Out-
Slave In (MOSI), Master In-Slave Out (MISO), or Serial Data (SDAT).
The SPI communications is as follows:
Command Direction (bit 7) = “1” enables SPI write transaction. A “0” enables SPI read transactions.
Command Increment (bit 6) = “1” enables SPI auto address increment. When set, the address field automatically
increments at the end of each data byte in a burst access, otherwise the same address is accessed.
Six bits of address.
Eight bits of data.
The device receives SCK from an application MCU on the SCK pin. Data from the application MCU is shifted in on the MOSI
pin. Data to the application MCU is shifted out on the MISO pin. The active-low Slave Select (
) pin must be asserted to
initiate an SPI transfer.
The application MCU can initiate SPI data transfers via a multi byte transaction. The first byte is the Command/Address byte,
and the following bytes are the data bytes as shown in Figure 2 through Figure 5.
Artaflex Inc.
215 Konrad Crescent
Markham, Ontario, Canada
L3R8T9
905-479-0148
DS-102-0006-R1.5
Revised 04 Jan 2013
Page 5 of 13
http://www.artaflexmodules.com
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