HEF4030B
Quad 2-input EXCLUSIVE-OR gate
Rev. 4 — 13 November 2013
Product data sheet
1. General description
The HEF4030B is a quad 2-input EXCLUSIVE-OR gate. The outputs are fully buffered for
the highest noise immunity and pattern insensitivity to output impedance.
It operates over a recommended V
DD
power supply range of 3 V to 15 V referenced to V
SS
(usually ground). Unused inputs must be connected to V
DD
, V
SS
, or another input.
2. Features and benefits
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Specified from
40 C
to +125
C
Complies with JEDEC standard JESD 13-B
Inputs and outputs are protected against electrostatic effects
3. Ordering information
Table 1.
Ordering information
All types operate from
40
C to +125
C
Type number
HEF4030BP
HEF4030BT
Package
Name
DIP14
SO14
Description
plastic dual in-line package; 14 leads (300 mil)
plastic small outline package; 14 leads; body width 3.9 mm
Version
SOT27-1
SOT108-1
4. Functional diagram
A
Y
B
mna788
Fig 1.
Functional diagram
Fig 2.
Logic diagram (one gate)
NXP Semiconductors
HEF4030B
Quad 2-input EXCLUSIVE-OR gate
5. Pinning information
5.1 Pinning
Fig 3.
Pin configuration
5.2 Pin description
Table 2.
Symbol
1A, 2A, 3A, 4A
1B, 2B, 3B, 4B
1Y, 2Y, 3Y, 4Y
V
SS
V
DD
Pin description
Pin
1, 5, 8, 12
2, 6, 9, 13
3, 4, 10, 11
7
14
Description
data input
data input
data output
ground (0 V)
supply voltage
6. Functional description
Table 3.
Input
nA
L
L
H
H
[1]
Functional table
[1]
Output
nB
L
H
L
H
nY
L
H
H
L
H = HIGH voltage level; L = LOW voltage level
HEF4030B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4 — 13 November 2013
2 of 12
NXP Semiconductors
HEF4030B
Quad 2-input EXCLUSIVE-OR gate
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to V
SS
= 0 V (ground).
Symbol
V
DD
I
IK
V
I
I
OK
I
I/O
I
DD
T
stg
T
amb
P
tot
Parameter
supply voltage
input clamping current
input voltage
output clamping current
input/output current
supply current
storage temperature
ambient temperature
total power dissipation
T
amb
=
40 C
to + 125
C
DIP14
SO14
P
[1]
[2]
[1]
[2]
Conditions
V
I
<
0.5
V or V
I
> V
DD
+ 0.5 V
V
O
<
0.5
V or V
O
> V
DD
+ 0.5 V
Min
0.5
-
0.5
-
-
-
65
40
-
-
-
Max
+18
10
V
DD
+ 0.5
10
10
50
+150
+125
750
500
100
Unit
V
mA
V
mA
mA
mA
C
C
mW
mW
mW
power dissipation
per output
For DIP14 packages: above T
amb
= 70
C,
P
tot
derates linearly with 12 mW/K.
For SO14 packages: above T
amb
= 70
C,
P
tot
derates linearly with 8 mW/K.
8. Recommended operating conditions
Table 5.
Symbol
V
DD
V
I
T
amb
t/V
Recommended operating conditions
Parameter
supply voltage
input voltage
ambient temperature
input transition rise and fall rate
in free air
V
DD
= 5 V
V
DD
= 10 V
V
DD
= 15 V
Conditions
Min
3
0
40
-
-
-
Typ
-
-
-
-
-
-
Max
15
V
DD
+125
3.75
0.5
0.08
Unit
V
V
C
s/V
s/V
s/V
HEF4030B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4 — 13 November 2013
3 of 12
NXP Semiconductors
HEF4030B
Quad 2-input EXCLUSIVE-OR gate
9. Static characteristics
Table 6.
Static characteristics
V
SS
= 0 V; V
I
= V
SS
or V
DD
; unless otherwise specified.
Symbol Parameter
V
IH
HIGH-level
input voltage
Conditions
I
O
< 1
A
V
DD
5V
10 V
15 V
V
IL
LOW-level
input voltage
I
O
< 1
A
5V
10 V
15 V
V
OH
HIGH-level
output voltage
I
O
< 1
A
5V
10 V
15 V
V
OL
LOW-level
output voltage
I
O
< 1
A
5V
10 V
15 V
I
OH
HIGH-level
output current
V
O
= 2.5 V
V
O
= 4.6 V
V
O
= 9.5 V
V
O
= 13.5 V
I
OL
LOW-level
output current
V
O
= 0.4 V
V
O
= 0.5 V
V
O
= 1.5 V
I
I
I
DD
input leakage
current
supply current
5V
5V
10 V
15 V
5V
10 V
15 V
15 V
all valid input 5 V
combinations; 10 V
I
O
= 0 A
15 V
T
amb
=
40 C
T
amb
= +25
C
T
amb
= +85
C
T
amb
= +125
C
Unit
Min
3.5
7.0
11.0
-
-
-
4.95
9.95
14.95
-
-
-
-
-
-
-
0.64
1.6
4.2
-
-
-
-
-
Max
-
-
-
1.5
3.0
4.0
-
-
-
0.05
0.05
0.05
1.7
0.64
1.6
4.2
-
-
-
0.1
0.25
0.5
1.0
-
Min
3.5
7.0
11.0
-
-
-
4.95
9.95
14.95
-
-
-
-
-
-
-
0.5
1.3
3.4
-
-
-
-
-
Max
-
-
-
1.5
3.0
4.0
-
-
-
0.05
0.05
0.05
1.4
0.5
1.3
3.4
-
-
-
0.1
0.25
0.5
1.0
7.5
Min
3.5
7.0
11.0
-
-
-
4.95
9.95
14.95
-
-
-
-
-
-
-
0.36
0.9
2.4
-
-
-
-
-
Max
-
-
-
1.5
3.0
4.0
-
-
-
0.05
0.05
0.05
1.1
0.36
0.9
2.4
-
-
-
1.0
7.5
15.0
30.0
-
Min
3.5
7.0
11.0
-
-
-
4.95
9.95
14.95
-
-
-
-
-
-
-
0.36
0.9
2.4
-
-
-
-
-
Max
-
-
-
1.5
3.0
4.0
-
-
-
0.05
0.05
0.05
1.1
0.36
0.9
2.4
-
-
-
1.0
7.5
15.0
30.0
-
V
V
V
V
V
V
V
V
V
V
V
V
mA
mA
mA
mA
mA
mA
mA
A
A
A
A
pF
C
I
input
capacitance
HEF4030B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4 — 13 November 2013
4 of 12
NXP Semiconductors
HEF4030B
Quad 2-input EXCLUSIVE-OR gate
10. Dynamic characteristics
Table 7.
Dynamic characteristics
T
amb
= 25
C; for waveforms see
Figure 4;
for test circuit, see
Figure 5;
unless otherwise specified.
Symbol Parameter
t
PHL
HIGH to LOW propagation delay
Extrapolation formula
[1]
57 + 0.55
C
L
24 + 0.23
C
L
22 + 0.16
C
L
t
PLH
LOW to HIGH propagation delay
47 + 0.55
C
L
19 + 0.23
C
L
17 + 0.16
C
L
t
THL
HIGH to LOW output transition time 10 + 1.00
C
L
9 + 0.42
C
L
6 + 0.28
C
L
t
TLH
LOW to HIGH output transition time 10 + 1.00
C
L
9 + 0.42
C
L
6 + 0.28
C
L
[1]
V
DD
5V
10 V
15 V
5V
10 V
15 V
5V
10 V
15 V
5V
10 V
15 V
Min
-
-
-
-
-
-
-
-
-
-
-
-
Typ
85
35
30
75
30
25
60
30
20
60
30
20
Max
175
75
55
150
65
50
120
60
40
120
60
40
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
The typical value of the propagation delay and output transition time can be calculated with the extrapolation formula (C
L
in pF).
Table 8.
Dynamic power dissipation
V
SS
= 0 V; t
r
= t
f
20 ns; T
amb
= 25
C.
Symbol Parameter
P
D
dynamic power dissipation
V
DD
5V
Typical formula
P
D
= 1100
f
i
+
(f
o
C
L
)
V
DD2
(W)
Where
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
10 V P
D
= 4900
f
i
+
(f
o
C
L
)
V
DD2
(W)
15 V P
D
= 14400
f
i
+
(f
o
C
L
)
V
DD2
(W) C
L
= output load capacitance in pF;
(f
o
C
L
) = sum of the outputs;
V
DD
= supply voltage in V.
HEF4030B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4 — 13 November 2013
5 of 12
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