Operated at Commercial and Industrial Temperature Ranges.
Preliminary
CMOS SRAM
Revision History
Rev No.
Rev. 0.0
Rev. 1.0
History
Initial release with Preliminary.
1.1 Removed Low power Version.
1.2 Removed Data Retention Characteristics
1.3 Changed I
SB1
to 20mA
2.1 Relax D.C parameters.
Item
I
CC
12ns
15ns
20ns
Previous
190mA
185mA
180mA
Current
200mA
195mA
190mA
Draft Data
Feb. 12. 1999
Mar. 29. 1999
Remark
Preliminary
Preliminary
Rev. 2.0
Aug. 19. 1999
Preliminary
2.2 Relax Absolute Maximum Rating.
Item
Voltage on Any Pin Relative to Vss
Previous
-0.5 to 7.0
Current
-0.5 to Vcc+0.5
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
Rev 2.0
August 1999
PRELIMPreliminaryPPPPPPPPPINARY
K6R4016C1C-C, K6R4016C1C-I
256K x 16 Bit High-Speed CMOS Static RAM
FEATURES
• Fast Access Time 12,15,20ns(Max.)
• Low Power Dissipation
Standby (TTL)
: 70mA(Max.)
(CMOS) : 20mA(Max.)
Operating K6R4016C1C-12 : 200mA(Max.)
K6R4016C1C-15 : 195mA(Max.)
K6R4016C1C-20 : 190mA(Max.)
• Single 5.0V
±10%
Power Supply
• TTL Compatible Inputs and Outputs
• I/O Compatible with 3.3V Device
• Fully Static Operation
- No Clock or Refresh required
• Three State Outputs
• Center Power/Ground Pin Configuration
• Data Byte Control : LB : I/O1~ I/O8, UB : I/O9~ I/O16
• Standard Pin Configuration
K6R4016C1C-J : 44-SOJ-400
K6R4016C1C-T : 44-TSOP2-400BF
K6R4016C1C-F : 48-Fine pitch BGA with 0.75 Ball pitch
Preliminary
CMOS SRAM
GENERAL DESCRIPTION
The K6R4016C1C is a 4,194,304-bit high-speed Static Ran-
dom Access Memory organized as 262,144 words by 16 bits.
The K6R4016C1C uses 16 common input and output lines and
has an output enable pin which operates faster than address
access time at read cycle. Also it allows that lower and upper
byte access by data byte control(UB, LB). The device is fabri-
cated using SAMSUNG′s advanced CMOS process and
designed for high-speed circuit technology. It is particularly well
suited for use in high-density high-speed system applications.
The K6R4016C1C is packaged in a 400mil 44-pin plastic SOJ
or TSOP(II) forward or 48 Fine pitch BGA.
FUNCTIONAL BLOCK DIAGRAM
Clk Gen.
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
I/O
1
~I/O
8
I/O
9
~I/O
16
ORDERING INFORMATION
K6R4016C1C-C12/C15/C20
Commercial Temp.
Industrial Temp.
K6R4016C1C-I12/I15/I20
Pre-Charge Circuit
Row Select
Memory Array
1024 Rows
256 x 16 Columns
Data
Cont.
Data
Cont.
Gen.
CLK
I/O Circuit &
Column Select
A
10
A
11
A
12
A
13
A
14
A
15
A
16
A
17
WE
OE
UB
LB
CS
-2-
Rev 2.0
August 1999
PRELIMPreliminaryPPPPPPPPPINARY
K6R4016C1C-C, K6R4016C1C-I
PIN CONFIGURATION
(Top View)
1
2
3
4
5
6
Preliminary
CMOS SRAM
A
0
A
1
A
2
A
3
A
4
CS
I/O
1
I/O
2
I/O
3
1
2
3
4
5
6
7
8
9
44 A
17
43 A
16
42 A
15
41 OE
40 UB
39 LB
38 I/O
16
37 I/O
15
36 I/O
14
D
Vss
I/O4
A17
A7
I/O12
Vcc
C
I/O2
I/O3
A5
A6
I/O11
I/O10
B
I/O1
UB
A3
A4
CS
I/O9
A
LB
OE
A0
A1
A2
N.C
I/O
4
10
Vcc 11
Vss 12
I/O
5
13
I/O
6
14
I/O
7
15
I/O
8
16
WE 17
A
5
18
A
6
19
A
7
20
A
8
21
A
9
22
SOJ/
TSOP2
35 I/O
13
34 Vss
33 Vcc
32 I/O
12
31 I/O
11
30 I/O
10
29 I/O
9
28 N.C
27 A
14
26 A
13
25 A
12
24 A
11
23 A
10
H
N.C
A8
A9
A10
A11
N.C
G
I/O8
N.C
A12
A13
WE
I/O16
F
I/O7
I/O6
A14
A15
I/O14
I/O15
E
Vcc
I/O5
N.C
A16
I/O13
Vss
48-CSP
PIN FUNCTION
Pin Name
A
0
- A
17
WE
CS
OE
LB
UB
I/O
1
~ I/O
16
V
CC
V
SS
N.C
Pin Function
Address Inputs
Write Enable
Chip Select
Output Enable
Lower-byte Control(I/O
1
~I/O
8
)
Upper-byte Control(I/O
9
~I/O
16
)
Data Inputs/Outputs
Power(+5.0V)
Ground
No Connection
ABSOLUTE MAXIMUM RATINGS*
Parameter
Voltage on Any Pin Relative to V
SS
Voltage on V
CC
Supply Relative to V
SS
Power Dissipation
Storage Temperature
Operating Temperature
Commercial
Industrial
Symbol
V
IN
, V
OUT
V
CC
P
D
T
STG
T
A
T
A
Rating
-0.5 to V
CC
+0.5
-0.5 to 7.0
1.0
-65 to 150
0 to 70
-40 to 85
Unit
V
V
W
°C
°C
°C
*
Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
-3-
Rev 2.0
August 1999
PRELIMPreliminaryPPPPPPPPPINARY
K6R4016C1C-C, K6R4016C1C-I
RECOMMENDED DC OPERATING CONDITIONS*
(T
A
=0 to 70°C)
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Symbol
V
CC
V
SS
V
IH
V
IL
Min
4.5
0
2.2
-0.5**
Typ
5.0
0
-
-
Max
5.5
0
V
CC
+0.5***
0.8
Unit
V
V
V
V
Preliminary
CMOS SRAM
* The above parameters are also guaranteed at industrial temperature range.
** V
IL
(Min) = -2.0V a.c(Pulse Width
≤
8ns) for I
≤
20mA
.
*** V
IH
(Max) = V
CC
+ 2.0V a.c (Pulse Width
≤
8ns) for I
≤
20mA.
DC AND OPERATING CHARACTERISTICS*
(T
A
=0 to 70°C, Vcc= 5.0V±10%, unless otherwise specified)
Parameter
Input Leakage Current
Output Leakage Current
Operating Current
Symbol
I
LI
I
LO
I
CC
V
IN
=V
SS
to V
CC
CS=V
IH
or OE=V
IH
or WE=V
IL
V
OUT
= V
SS
to V
CC
Min. Cycle, 100% Duty
CS=V
IL,
V
IN
=V
IH
or V
IL,
I
OUT
=0mA
12ns
15ns
20ns
Standby Current
I
SB
I
SB1
Output Low Voltage Level
Output High Voltage Level
V
OL
V
OH
V
OH1**
Min. Cycle, CS=V
IH
f=0MHz, CS≥V
CC
-0.2V,
V
IN
≥V
CC
-0.2V or V
IN
≤0.2V
I
OL
=8mA
I
OH
=-4mA
I
OH1
=-0.1mA
Test Conditions
Min
-2
-2
-
-
-
-
-
-
2.4
-
Max
2
2
200
195
190
70
20
0.4
-
3.95
V
V
V
mA
Unit
µA
µA
mA
* The above parameters are also guaranteed at industrial temperature range.
** V
CC
=5.0V±5%
,
Temp.=25°C.
CAPACITANCE*
(T
A
=25°C, f=1.0MHz)
Item
Input/Output Capacitance
Input Capacitance
* Capacitance is sampled and not 100% tested.
Symbol
C
I/O
C
IN
Test Conditions
V
I/O
=0V
V
IN
=0V
MIN
-
-
Max
8
7
Unit
pF
pF
-4-
Rev 2.0
August 1999
PRELIMPreliminaryPPPPPPPPPINARY
K6R4016C1C-C, K6R4016C1C-I
AC CHARACTERISTICS
(T
A
=0 to 70°C, V
CC
=5.0V±10%, unless otherwise noted.)
TEST CONDITIONS*
Parameter
Input Pulse Levels
Input Rise and Fall Times
Input and Output timing Reference Levels
Output Loads
* The above test conditions are also applied at industrial temperature range.
Preliminary
CMOS SRAM
Value
0V to 3V
3ns
1.5V
See below
Output Loads(A)
Output Loads(B)
for t
HZ
, t
LZ
, t
WHZ
, t
OW
, t
OLZ
& t
OHZ
+5.0V
R
L
= 50Ω
D
OUT
V
L
= 1.5V
Z
O
= 50Ω
30pF*
480Ω
D
OUT
255Ω
5pF*
* Capacitive Load consists of all components of the
test environment.
* Including Scope and Jig Capacitance
READ CYCLE*
K6R4016C1C-12
K6R4016C1C-15
K6R4016C1C-20
Parameter
Read Cycle Time
Address Access Time
Chip Select to Output
Output Enable to Valid Output
UB, LB Access Time
Chip Enable to Low-Z Output
Output Enable to Low-Z Output
UB, LB Enable to Low-Z Output
Chip Disable to High-Z Output
Output Disable to High-Z Output
UB, LB Disable to High-Z Output
Output Hold from Address Change
Symbol
t
RC
t
AA
t
CO
t
OE
t
BA
t
LZ
t
OLZ
t
BLZ
t
HZ
t
OHZ
t
BHZ
t
OH
Min
12
-
-
-
-
3
0
0
0
0
0
3
Max
-
12
12
6
6
-
-
-
6
6
6
-
Min
15
-
-
-
-
3
0
0
0
0
0
3
Max
-
15
15
7
7
-
-
-
7
7
7
-
Min
20
-
-
-
-
3
0
0
0
0
0
3
Max
-
20
20
9
9
-
-
-
9
9
9
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
* The above parameters are also guaranteed at industrial temperature range.
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