S26KS512SDGBHM033 datasheet, PDF

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S26KS512SDGBHM033: DescriptionFlash, 64MX8, 96ns, PBGA24, FBGA-24; Categorystorage storage; File Size3MB，102 Pages; ManufacturerCypress Semiconductor

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S26KS512SDGBHM033 Overview

Flash, 64MX8, 96ns, PBGA24, FBGA-24

S26KS512SDGBHM033 Parametric

Parameter Name	Attribute value
Objectid	8235566026
package instruction	VBGA,
Reach Compliance Code	compliant
ECCN code	EAR99
Maximum access time	96 ns
JESD-30 code	R-PBGA-B24
length	8 mm
memory density	536870912 bit
Memory IC Type	FLASH
memory width	8
Number of functions	1
Number of terminals	24
word count	67108864 words
character code	64000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	125 °C
Minimum operating temperature	-40 °C
organize	64MX8
Package body material	PLASTIC/EPOXY
encapsulated code	VBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, VERY THIN PROFILE
Parallel/Serial	PARALLEL
Programming voltage	1.8 V
Filter level	AEC-Q100; TS 16949
Maximum seat height	1 mm
Maximum supply voltage (Vsup)	1.95 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	AUTOMOTIVE
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
width	6 mm

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Please note that Cypress is an Infineon Technologies Company.

The document following this cover page is marked as “Cypress” document as this is the

company that originally developed the product. Please note that Infineon will continue

to offer the product to new and existing customers as part of the Infineon product

portfolio.

Continuity of document content

The fact that Infineon offers the following product as part of the Infineon product

portfolio does not lead to any changes to this document. Future revisions will occur

when appropriate, and any changes will be set out on the document history page.

Continuity of ordering part numbers

Infineon continues to support existing part numbers. Please continue to use the

ordering part numbers listed in the datasheet for ordering.

www.infineon.com

S26KL512S/S26KS512S

S26KL256S/S26KS256S

S26KL128S/S26KS128S

General Description



The Cypress HyperFlash family of products are high-speed CMOS, MirrorBit



NOR flash devices with the HyperBus low signal

count DDR interface, that achieves high speed read throughput. The DDR protocol transfers two data bytes per clock cycle on the

data (DQ) signals. A read or write access for the HyperFlash consists of a series of 16-bit wide, one clock cycle data transfers at the

internal HyperFlash core and two corresponding 8-bit wide, one-half-clock-cycle data transfers on the DQ signals.

Both data and command/address information are transferred in DDR fashion over the 8-bit data bus. The clock input signals are

used for signal capture by the HyperFlash device when receiving command/address/data information on the DQ signals. The Read

Data Strobe (RWDS) is an output from the HyperFlash device that indicates when data is being transferred from the memory to the

host. RWDS is referenced to the rising and falling edges of CK during the data transfer portion of read operations.

Command/address/write-data values are center aligned with the clock edges and read-data values are edge aligned with the

transitions of RWDS.

Read and write operations to the HyperFlash device are burst oriented. Read transactions can be specified to use either a wrapped

or linear burst. During wrapped operation, accesses start at a selected location and continue for a configured number of locations in

a group wrap sequence. During linear operation accesses start at a selected location and continue in a sequential manner until the

read operation is terminated, when CS# returns HIGH. Write transactions transfer one or more16-bit values.

Figure 1. Logic Block Diagram

Mandatory Signals

CS#

CK#

DQ[7:0]

RWDS

Optional Signals

CONTROL

LOGIC

ADDR

RESET#

RSTO#

INT#

PSC

PSC#

D E

E CC

C D

D EE

E RR

R S

Memory

Array

MIRRORBIT

Array

MEMORY ARRAY

Sense Amplifiers

SENSE AMPLIFIERS

Y DECODERS

Data Latch

ADDRESS

RWDS

GENERATOR

ADDR

The HyperFlash family consists of multiple densities, 1.8V/3.0V core and I/O, nonvolatile, synchronous flash memory devices. These

devices have an 8-bit (1-byte) wide DDR data bus and use only word-wide (16-bit data) address boundaries. Read operations

provide 16 bits of data during each clock cycle (8 bits on each clock edge). Write operations take 16 bits of data from each clock

cycle (8 bits on each clock edge).

Each random read accesses a 32-byte length and aligned set of data called a page. Each page consists of a pair of 16-byte aligned

groups of array data called half-pages. Half-pages are aligned on 16-byte address boundaries. A read access requires two clock

cycles to define the target half-page address and the burst type, then an additional initial latency. During the initial latency period the

third clock cycle will specify the starting address within the target half-page. After the initial data value has been output, additional

data can be read from the Page on subsequent clock cycles in either a wrapped or linear manner. When configured in linear burst

mode, while a page is being burst out, the device will automatically fetch the next sequential page from the MirrorBit flash memory

array. This simultaneous burst output while fetching from the array allows for a linear sequential burst operation that can provide a

sustained output of 333 MBps data rate [1-byte

(8-bit data bus) * 2 (Data on both clock edges) * 166 MHz = 333 MBps].

Document Number: 001-99198 Rev. *M

Page 4 of 101

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