SPT9110
100 MSPS SINGLE-TO-DIFFERENTIAL TRACK-AND-HOLD
FEATURES
• 400 MHz Sampling Bandwidth
• 100 MHz Sampling Rate
• Excellent Hold Mode Distortion
-66 dB @ 50 MSPS (f
IN
= 25 MHz)
-58 dB @ 100 MSPS (f
IN
= 50 MHz)
• Track Mode Slew Rate: 700 V/µs
• Low Power: 120 mW Differential Mode
75 mW Single-Ended Mode
• Single +5 V Supply
• Internal +2.5 V Reference
APPLICATIONS
•
•
•
•
THA for Differential ADCs
RF Demodulation Systems
Test Instrumentation
Digital Sampling Oscilloscopes
GENERAL DESCRIPTION
The SPT9110 is a single-to-differential track-and-hold ampli-
fier. It can be operated as a single-end THA only or, in full
configuration, as a single-to-differential THA. An internal
reference provides the common-mode voltage for the single-
to-differential output stage. The THA, inverter and reference
have separate power supply pins so each can be optionally
powered up and used.
This device provides an analog designer with a low cost
single-to-differential THA amplifier for interfacing differential
and single-ended ADCs.
The SPT9110 is offered in a 28-lead SOIC package in the
industrial temperature range.
BLOCK DIAGRAM
AVCC
(THA)
AVCC
Out+
(INV)
Analog In
(VIN)
1X
1X
Invert InA
CH
OLD
1 kΩ
R1
1 kΩ
R2
-
Out-
+
Invert InB
+2.5 V
Reference
CLK NCLK
AVCC
(Ref)
Ref
Out
Ref
In
AGND
ABSOLUTE MAXIMUM RATING (Beyond which damage may occur)
1
Supply Voltages
AV
CC
Supplies ............................................. -0.5 to +6 V
Input Voltages
Analog Input Voltage .................................... -0.5 to +6 V
CLK, NCLK Input .......................................... -0.5 to +6 V
Ref In ............................................................ -0.5 to +6 V
Output Currents
2
Continuous Output Current .................................
±15
mA
Temperature
Operating Temperature .............................. -40 to +85
°C
Junction Temperature ......................................... +150
°C
Lead, Soldering (10 seconds) ............................. +220
°C
Storage ..................................................... -65 to +150
°C
Note 1: Operation at any Absolute Maximum Ratings is not implied. See Electrical Specifications for proper nominal
applied conditions in typical application.
Note 2: Outputs are short circuit protected.
ELECTRICAL SPECIFICATIONS
AV
CC
= +5.0 V, AGND = 0.0 V, Output Load = 1 kΩ and 10 pF, V
IN
= 2.0 Vp-p,Internal Reference, unless otherwise specified.
PARAMETERS
DC Performance
Gain
∆V
IN
= 2.0 Vp-p
Single Ended Out
Differential Out
Offset V
IN
= +2.5 V
Out+
Differential
1
Output Drive Capacity
2
Output Load at 10 pF
Analog Input/Output
Output Voltage Range
Input Capacitance
Input Resistance
Reference Voltage Output
Reference Output Current
3
Reference Voltage Tempco
Clock Inputs
Input Type/Logic Family
Input Bias Current
Input Low Voltage (Differential)
Input High Voltage (differential)
TEST
CONDITIONS
TEST
LEVEL
MIN
SPT9110
TYP
MAX
UNITS
+25
°C
Full Temperature
+25
°C
Full Temperature
+25
°C
Full Temperature
+25
°C,
Ref In=Out+ CM
Full Temperature
Full Temperature
Full Temperature
Full Temperature
+25
°C
+25
°C
+25
°C
Full Temperature
I
V
I
V
I
V
I
V
IV
V
VI
V
I
I
V
V
V
I
I
I
0.95
1.80
0.97
0.96
1.93
1.92
±50
55
±5
10
±1
1
0.99
2.00
V/V
V/V
V/V
V/V
mV
mV
mV
mV
mA
kΩ
V
pF
kΩ
V
µA
ppm/°C
-100
-15
+100
±15
±10
1.5
100
2.35
5
140
2.45
±100
75
3.5
2.55
+25
°C
+25
°C
+25
°C
Differential PECL
2
3.3
3.9
4.1
10
3.5
µA
V
V
1
Differential offset is specified with Ref In equal to the common mode output voltage of OUT+ and so includes the offset error of the
inverter only.
2
This part is intended to drive a high impedance load. AC performance is degraded at
±10
mA. See the Typical Performance Graphs.
3
Ref Out has a typical output impedance of 1 kΩ and should be buffered for driving loads other than Ref In.
SPT9110
2
11/12/98
ELECTRICAL SPECIFICATIONS
AV
CC
= +5.0 V, AGND = 0.0 V, Output Load = 1 kΩ and 10 pF, V
IN
= 2.0 Vp-p,Internal Reference, unless otherwise specified.
PARAMETERS
Track Mode Dynamics
Bandwidth (-3 dB)
Single Ended Out
Differential Out
Slew Rate 2.0 Vp-p Output Step
Single Ended Out
Differential Out
7
Input RMS Spectral Noise
Track-to-Hold Switching
Aperture Delay
Aperture Jitter
Pedestal Offset
Hold Mode Dynamics
4
(V
IN
= 1 Vp-p)
Worst Harmonic
5 MHz, 50 MSPS, Single-Ended
Worst Harmonic
5 MHz, 50 MSPS, Differential
Worst Harmonic
25 MHz, 50 MSPS, Single-Ended
Worst Harmonic
25 MHz, 50 MSPS, Differential
Worst Harmonic
50 MHz, 100 MSPS, Single-Ended
Worst Harmonic
50 MHz, 100 MSPS, Differential
Sampling Bandwidth
5
(-3 dB)
V
IN
= 2.0 Vp-p
Hold Noise
6
(RMS)
Droop Rate, V
IN
= +2.5 V
Feedthrough Rejection (50 MHz)
V
IN
= 2 Vp-p
TEST
CONDITIONS
+25
°C
TEST
LEVEL
MIN
SPT9110
TYP
MAX
UNITS
V
V
+25
°C
20 pF Load
20 pF Load
Single Ended
Differential
+25
°C
+25
°C
+25
°C
Full Temperature
220
140
580
800
3.5
13.0
250
<1
±12
±12
MHz
MHz
V/µs
V/µs
nV/
Hz
IV
IV
V
V
V
V
IV
V
nV/
Hz
ps
ps rms
mV
mV
T
A
= +25
°C
T
A
= -40
°C
to +85
°C
T
A
= +25
°C
T
A
= -40
°C
to +85
°C
T
A
= +25
°C
T
A
= -40
°C
to +85
°C
T
A
= +25
°C
T
A
= -40
°C
to +85
°C
T
A
= +25
°C
T
A
= -40
°C
to +85
°C
T
A
= +25
°C
T
A
= -40
°C
to +85
°C
+25
°C
+25
°C
+25
°C
Full Temperature
Full Temperature
IV
V
IV
V
V
V
V
V
IV
V
IV
V
V
V
IV
IV
V
-64
-68
-64
-65
-63
-66
-63
-64
-60
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
MHz
mV/s
mV/µs
mV/µs
dB
-61
-54
-58
-54
-54
-50
400
300 x t
H
±40
±80
-65
-50
4. For hold times longer than 50 ns, the input common mode voltage may affect the hold mode distortion. (This is due to nonlinear
droop that varies with VCM.) For optimal performance, CADEKA recommends that the held output signal be used within 50 ns of the
application of the hold signal.
5. Sampling bandwidth is defined as the -3 dB frequency response of the input sampler to the hold capacitor when operating in the
sampling mode. It is greater than tracking bandwidth because it does not include the bandwidth of the output amplifier.
6. Hold mode noise is proportional to the length of time a signal is held. This value must be combined with the track mode noise to
obtain total noise.
7. Optimized for hold mode performance and low power.
SPT9110
3
11/12/98
ELECTRICAL SPECIFICATIONS
AV
CC
= +5.0 V, AGND = 0.0 V, R
Load
= 1 kΩ and 10 pF, V
IN
= 2.0 Vp-p, Internal Reference, unless otherwise specified.
PARAMETERS
Hold-to-Track Switching
8
Acquisition Time to 0.1%
1 V Output Step
Acquisition Time to 0.025%
1 V Output Step
Power Supplies
Supply Voltage
Supply Current
Single Ended Output Mode
9
Differential Output Mode
Power Dissipation
Single Ended Output Mode
9
Differential Output Mode
Power Supply Rejection Ratio
Single-Ended Output
8. Measured at the hold capacitor.
9. Inverter powered down.
TEST
CONDITIONS
+25
°C
+25
°C
TEST
LEVEL
V
V
MIN
SPT9110
TYP
3.5
4.0
MAX
UNITS
ns
ns
IV
I
4.75
5
15
24
75
120
44
5.25
20
30
100
150
V
mA
mA
mW
mW
dB
I
I
+25
°C
∆V
CC
= 0.5 V
P-P
I
V
TEST LEVEL CODES
All electrical characteristics are subject to the
following conditions: All parameters having min/
max specifications are guaranteed. The Test
Level column indicates the specific device test-
ing actually performed during production and
Quality Assurance inspection. Any blank sec-
tion in the data column indicates that the speci-
fication is not tested at the specified condition.
TEST LEVEL
I
II
III
IV
V
VI
TEST PROCEDURE
100% production tested at the specified temperature.
100% production tested at T
A
= +25
°C,
and sample
tested at the specified temperatures.
QA sample tested only at the specified temperatures.
Parameter is guaranteed (but not tested) by design
and characterization data.
Parameter is a typical value for information purposes
only.
100% production tested at T
A
= +25
°C.
Parameter is
guaranteed over specified temperature range.
SPT9110
4
11/12/98
TIMING SPECIFICATION DEFINITIONS
ACQUISITION TIME
This is the time it takes the SPT9110 to acquire the analog
signal at the internal hold capacitor when it makes a transition
from hold mode to track mode. (See figure 1.) The acquisition
time is measured from the 50% input clock transition point to
the point when the signal is within a specified error band at the
internal hold capacitor (ahead of the output amplifier). It does
not include the delay and settling time of the output amplifier.
Because the signal is internally acquired and settled at the
hold capacitor before the output voltage has settled, the
sampler can be put in hold mode before the output has settled.
TRACK-TO-HOLD SETTLING TIME
The time required for the output to settle to within 4 mV of its
final value.
APERTURE DELAY
The aperture delay time is the interval between the leading
edge transition of the clock input and the instant when the
input signal was equal to the held value. It is the difference
in time between the digital hold switch delay and the analog
signal propagation time.
Figure 1 - Timing Diagram
Aperture
Delay
Input
Acquisition
Time
Observed at
Hold Capacitor
Output
Observed at
Amplifier Output
Track-to-Hold
Settling
CLK
Hold
Track
Hold
NCLK
SPT9110
5
11/12/98
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