FEDL22Q553-02
Issue Date: Apr. 25, 2013
ML22Q553-NNNMB/ML22Q553-xxxMB
4-Channel Mixing Speech Synthesis LSI with Built-in FLASH ROM for Automotive
GENERAL DESCRIPTION
The ML22Q553-NNN and ML22Q553-xxx are 4-channel mixing speech synthesis LSIs with built-in FLASH
ROM for voice data. These LSIs incorporate into them an HQ-ADPCM decoder that enables high sound
quality, 16-bit D/A converter, low-pass filter, 1.0 W monaural speaker amplifier for driving speakers , and
over-current detectible function for Speaker Pins. Since functions necessary for voice output are all integrated
into a single chip, a system can be upgraded with audio features by only using one of these LSIs.
•
Capacity of internal memory and the maximum voice production time (when HQ-ADPCM
※
1
method used)
Maximum voice production time (sec)
f
sam
= 8.0 kHz
ML22Q553-NNN/-xxx
4 Mbits
161
f
sam
= 16.0 kHz
80
f
sam
= 32.0 kHz
40
Product name
ROM capacity
FEATURES
Can be specified for each phrase.
HQ-ADPCM / 8-bit non-linear PCM / 8-bit PCM / 16-bit PCM
•
Sampling frequency:
Can be specified for each phrase.
12.0/24.0/48.0 kHz, 8.0/16.0/32.0 kHz, 6.4/12.8/25.6 kHz
•
Built-in low-pass filter and 16-bit D/A converter
•
Built-in speaker driver amplifier:
1.0 W, 8Ω (at DV
DD
= 5 V)
(with over-current detectible function for Speaker pins)
•
External analog voice input (built-in analog mixing function)
•
CPU command interface:
Clock synchronous serial interface
•
Maximum number of phrases:
1024 phrases, from 000h to 3FFh
•
Edit ROM
•
Volume control:
CVOL command: Adjustable through 32 levels (including OFF)
AVOL command: Adjustable through 50 levels (including OFF)
•
Repeat function:
LOOP command
•
Channe½ mixing function:
4 channels
•
Power supply voltage detection function: Can be controlled at six levels from 2.7 to 4.0 V (including the
OFF setting)
•
Source oscillation frequency:
4.096 MHz
•
Power supply voltage:
4.5 to 5.5 V
•
Operating temperature range:
–40°C to +105°C
※
2
•
Package:
heat sink type 30-pin plastic SSOP(P-SSOP30-56-0.65-Z6K)
•Product
name:
ML22Q553-NNNMB/ML22Q553-xxxMB
(“xxx” denotes ROM code number)
※1
HQ-ADPCM is a high sound quality audio compression technology of "Ky's".
“Ｋ½’½” is a Registered trademark of National Universities corporate Kyushu
Institute of Technology
•
Speech synthesis method:
※2
The limitation on the operation time changes by the using condition. (Refer to Page66)
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FEDL22Q553-02
ML22Q553
PIN DESCRIPTION (1)
Pin
1
2
Symbol
AIN
SG
I/O Attribute
I
—
Description
Attribute
analog
analog
Initial
value
0
0
3
V
DDR
4,18
5,15
6
DV
DD
DGND
V
DDL
7
DIPH
8
9
STATUS
ERR
10
11
CSB
SCK
12
SI
13
SO
Speaker amplifier input pin.
Built-in speaker amplifier’s reference voltage output pin.
O
—
Connect a capacitor of 0.1
μF
or more between this pin and
DGND.
2.5 V regulator output pin.
O
—
Acts as an internal power supply (for ROM). Connect a
capacitor of 10
μF
or more between this pin and DGND.
Digital power supply pin.
—
—
Connect a bypass capacitor of 10μF or more between this
pin and DGND.
—
—
Digital ground pin
2.5 V regulator output pin.
O
—
Acts as an internal power supply (for logic). Connect a
capacitor of 10
μF
or more between this pin and DGND.
Serial interface switching pin.
Pin for choosing between rising edges and falling edges as
to the edges of the SCK pulses used for shifting serial data
input to the SI pin into the inside of the LSI.
When this pin is at a “L” level, SI input data is shifted into the
LSI on the rising edges of the SCK clock pulses and a status
I
Positive
signal is output from the SO pin on the falling edges of the
SCK clock pulses.
When this pin is at a “H” level, SI input data is shifted into the
LSI on the falling edges of the SCK clock pulses and a status
signal is output from the SO pin on the rising edges of the
SCK clock pulses.
Channel status output pin.
O Positive Outputs the BUSYB or NCR signal for each channel by
inputting the OUTSTAT command.
Error output pin.
O Positive
Outputs a “H” level if an error occurs.
Chip select pin.
A “L” level on this pin accepts the SCK or SI inputs. When
I Negative
this pin is at a “H” level, neither the SCK nor SI signal is input
to the LSI.
I
Positive Synchronous serial clock input pin.
Synchronous serial data input pin.
When the DIPH pin is at a “L” level, data is shifted in on the
I
—
rising edges of the SCK clock pulses.
When the DIPH pin is at a “H” level, data is shifted in on the
falling edges of the SCK clock pulses.
Channel status serial output pin.
Outputs a status signal on the falling edges of the SCK clock
pulses when the DIPH pin is at a ”L” level; outputs a status
signal on the rising edges of the SCK clock pulses when the
O Positive
DIPH pin is at a ”H” level.
When the CSB pin is at a ”L” level, the status of each channel
is output serially in sync with the SCK clock. When the CSB
pin is at a ”H” level, this pin goes into a high impedance state.
analog
0
power
gnd
power
—
—
0
digital
0
digital
digital
1
0
digital
clk
1
0
digital
0
digital
Hi-Z
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