RIAQ24TTEB432JEFC datasheet, PDF

RIAQ24TTEB432JEFC: DescriptionArray/Network Resistor, Isolated, Thin Film, 1W, 4300ohm, 100V, 5% +/-Tol, -25,25ppm/Cel, 3415,; CategoryPassive components The resistor; File Size217KB，2 Pages; ManufacturerKOA Speer; Websitehttp://www.koaspeer.com/; Environmental Compliance

Download Datasheet Parametric View All

RIAQ24TTEB432JEFC Overview

Array/Network Resistor, Isolated, Thin Film, 1W, 4300ohm, 100V, 5% +/-Tol, -25,25ppm/Cel, 3415,

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Objectid	735306108
Reach Compliance Code	compliant
ECCN code	EAR99
structure	Rectangular
JESD-609 code	e3
Network Type	Isolated
Number of terminals	24
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Package height	1.6 mm
Package length	8.66 mm
Package shape	RECTANGULAR PACKAGE
Package form	SMT
Package width	3.81 mm
method of packing	TR, 13 Inch
Rated power dissipation(P)	1 W
resistance	4300 Ω
Resistor type	ARRAY/NETWORK RESISTOR
series	R(X)A
size code	3415
technology	THIN FILM
Temperature Coefficient	-25,25 ppm/°C
Terminal surface	Matte Tin (Sn)
Tolerance	5%
Operating Voltage	100 V

【Xianji HPM6750 Review】Interim (Final) Summary: Time flies. It has been two months since I received the board. A few days ago, the administrator said that the progress will be finished on June 30. I was surprised that it was so fast. It felt like t...; littleshrimp Domestic Chip Exchange

Shortlist | 2020-2021 ON Semiconductor and Avnet IoT Creative Design Competition: [Competition Details] 2020-2021 ON Semiconductor and Avnet IoT Creative Design CompetitionThank you very much for your support of this competition!The finalists were selected by ON Semiconductor, Avne...; EEWORLD社区 onsemi and Avnet IoT Innovation Design Competition

FPGA_100 Days Journey_Key Debounce.pdf: FPGA_100 Days Journey_Key Debounce.pdf...; zxopenljx EE_FPGA Learning Park

CSM Code Security Module FAQ: Naming convention -- CSM: Code Security Module Code Security Module -- ECSL: Emulation Code Security Logic Emulation Code Security LogicFrequently asked questions Q: What happens when the CSM automati...; Jacktang Microcontroller MCU

FPGA implementation of DVI output image selection interception.pdf: FPGA implementation of DVI output image selection interception.pdf...; zxopenljx EE_FPGA Learning Park

ASIC Design-FPGA Prototype Verification: ASIC Design-FPGA Prototype Verification...; 雷北城 FPGA/CPLD

Shortcut: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

Popular Components