R5F101PKAFB#30 datasheet, PDF - EEWORLD Datasheet

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R5F101PKAFB#30: DescriptionR5F101PKAFB#30; CategoryThe embedded processor and controller Microcontrollers and processors; File Size3MB，200 Pages; ManufacturerRenesas Electronics Corporation; Websitehttps://www.renesas.com/; Environmental Compliance

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R5F101PKAFB#30 Overview

R5F101PKAFB#30

R5F101PKAFB#30 Parametric

Parameter Name	Attribute value
Brand Name	Renesas
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Objectid	7343329993
Parts packaging code	LFQFP
package instruction	LFQFP,
Contacts	100
Manufacturer packaging code	PLQP0100KE-A100
Reach Compliance Code	compliant
Factory Lead Time	20 weeks
Has ADC	YES
Address bus width
bit size	16
maximum clock frequency	20 MHz
DMA channel	YES
External data bus width
length	20 mm
Number of I/O lines	120
Number of terminals	128
PWM channel	YES
encapsulated code	LFQFP
Package shape	RECTANGULAR
Package form	FLATPACK, LOW PROFILE, FINE PITCH
speed	32 MHz
Maximum supply voltage	5.5 V
Minimum supply voltage	2.7 V
Nominal supply voltage	3 V
surface mount	YES
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
width	14 mm
uPs/uCs/peripheral integrated circuit type	MICROCONTROLLER

User Manual

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Datasheet

RL78/G13

RENESAS MCU

R01DS0131EJ0340

Rev.3.40

May 31, 2018

True Low Power Platform (as low as 66

A/MHz, and 0.57

A for RTC + LVD), 1.6 V to 5.5 V operation,

16 to 512 Kbyte Flash, 41 DMIPS at 32 MHz, for General Purpose Applications

1. OUTLINE

1.1 Features

Ultra-low power consumption technology



= single power supply voltage of 1.6 to 5.5 V



HALT mode



STOP mode



SNOOZE mode

RL78 CPU core



CISC architecture with 3-stage pipeline



Minimum instruction execution time: Can be changed

from high speed (0.03125 μs: @ 32 MHz operation

with high-speed on-chip oscillator) to ultra-low speed

(30.5 μs: @ 32.768 kHz operation with subsystem

clock)



Address space: 1 MB



General-purpose registers: (8-bit register × 8) × 4

banks



On-chip RAM: 2 to 32 KB

Code flash memory



Code flash memory: 16 to 512 KB



Block size: 1 KB



Prohibition of block erase and rewriting (security

function)



On-chip debug function



Self-programming (with boot swap function/flash shield

window function)

Data Flash Memory



Data flash memory: 4 KB to 8 KB



Back ground operation (BGO): Instructions can be

executed from the program memory while rewriting the

data flash memory.



Number of rewrites: 1,000,000 times (TYP.)



Voltage of rewrites: V

= 1.8 to 5.5 V

High-speed on-chip oscillator



Select from 32 MHz, 24 MHz, 16 MHz, 12 MHz, 8 MHz,

6 MHz, 4 MHz, 3 MHz, 2 MHz, and 1 MHz



High accuracy: +/- 1.0 % (V

= 1.8 to 5.5 V, T

= -20

to +85°C)

Operating ambient temperature



= -40 to +85°C (A: Consumer applications, D:

Industrial applications )



= -40 to +105°C (G: Industrial applications)

Power management and reset function



On-chip power-on-reset (POR) circuit



On-chip voltage detector (LVD) (Select interrupt and

reset from 14 levels)

DMA (Direct Memory Access) controller



2/4 channels



Number of clocks during transfer between 8/16-bit

SFR and internal RAM: 2 clocks

Multiplier and divider/multiply-accumulator



16 bits × 16 bits = 32 bits (Unsigned or signed)



32 bits ÷ 32 bits = 32 bits (Unsigned)



16 bits × 16 bits + 32 bits = 32 bits (Unsigned or

signed)

Serial interface



CSI: 2 to 8 channels



UART/UART (LIN-bus supported): 2 to 4 channels



C/Simplified I

C communication: 2 to 8 channels

Timer



16-bit timer: 8 to 16 channels



12-bit interval timer: 1 channel



Real-time clock:

1 channel (calendar for 99 years,

alarm function, and clock

correction function)



Watchdog timer:

1 channel (operable with the

dedicated low-speed on-chip

oscillator)

A/D converter



8/10-bit resolution A/D converter (V

= 1.6 to 5.5 V)



Analog input: 6 to 26 channels



Internal reference voltage (1.45 V) and temperature

sensor

Note 1

I/O port



I/O port: 16 to 120 (N-ch open drain I/O [withstand

voltage of 6 V]: 0 to 4, N-ch open drain I/O

withstand voltage

Note 2

/EV

withstand

voltage

Note 3

]: 5 to 25)



Can be set to N-ch open drain, TTL input buffer, and

on-chip pull-up resistor



Different potential interface: Can connect to a 1.8/2.5/3

V device



On-chip key interrupt function



On-chip clock output/buzzer output controller

Others



On-chip BCD (binary-coded decimal) correction circuit

Notes 1.

Can be selected only in HS (high-speed main)

mode

Products with 20 to 52 pins

Products with 64 to 128 pins

Remark

The functions mounted depend on the product.

See

1.6 Outline of Functions.

R01DS0131EJ0340 Rev.3.40

May 31, 2018

1 of 194

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