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LMUN5236T1G_15

Description
Bias Resistor Transistor
File Size202KB,10 Pages
ManufacturerLRC
Websitehttp://www.lrc.cn
Download Datasheet View All

LMUN5236T1G_15 Overview

Bias Resistor Transistor

LESHAN RADIO COMPANY, LTD.
Bias Resistor Transistor
NPN Silicon Surface Mount Transistor
with Monolithic Bias Resistor Network
This new series of digital transistors is designed to replace a single
device and its external resistor bias network. The BRT (Bias Resistor
Transistor) contains a single transistor with a monolithic bias network con-
sisting of two resistors; a series base resistor and a base–emitter resistor.
The BRT eliminates these individual components by integrating them into a
single device. The use of a BRT can reduce both system cost and board
space. The device is housed in the SC–70/SOT–323 package which is
designed for low power surface mount applications.
Simplifies Circuit Design
Reduces Board Space
Reduces Component Count
The SC–70/SOT–323 package can be soldered using wave or
LMUN5211T1G
Series
S-LMUN5211T1G
Series
3
1
2
SC-70 / SOT-323
PIN 1
BASE
(INPUT)
R
1
PIN 3
COLLECTOR
(OUTPUT)
R
2
PIN 2
EMITTER
(GROUND)
reflow. The modified gull–winged leads absorb thermal stress
during soldering eliminating the possibility of damage to the die.
• Available in 8 mm embossed tape and reel
Use the Device Number to order the 7 inch/3000 unit reel.
• Pb-Free package is available
•S- Prefix for Automotive and Other Applications Requiring Unique Site
and Control Change Requirements; AEC-Q101 Qualified and PPAP Capable.
DEVICE MARKING INFORMATION
See specific marking information in the device marking table on page 2
of this data sheet.
MARKINGDIAGRAM
8X
M
8x = Specific Device Code
x = (See Marking Table)
M= Date Code
MAXIMUM RATINGS
(T
A
= 25°C unless otherwise noted)
Rating
Collector-Base Voltage
Collector-Emitter Voltage
Collector Current
Symbol
V
CBO
V
CEO
I
C
Value
50
50
100
Unit
Vdc
Vdc
mAdc
THERMAL CHARACTERISTICS
Characteristic
Total Device Dissipation
T
A
= 25°C
Derate above 25°C
Thermal Resistance –
Junction-to-Ambient
Thermal Resistance –
Junction-to-Lead
Junction and Storage
Temperature Range
1. FR–4 @ Minimum Pad
2. FR–4 @ 1.0 x 1.0 inch Pad
Symbol
P
D
Max
202 (Note 1.)
310 (Note 2.)
1.6 (Note 1.)
2.5 (Note 2.)
618 (Note 1.)
403 (Note 2.)
280 (Note 1.)
332 (Note 2.)
–55 to +150
Unit
mW
mW/°C
°C/W
°C/W
°C
R
θJA
R
θJL
T
J,
T
stg
Rev.O 1/10

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Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
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