PLL/Frequency Synthesis Circuit,
Parameter Name | Attribute value |
package instruction | DIP-16 |
Reach Compliance Code | compliant |
Other features | SEATED HEIGHT CALCULATED |
Analog Integrated Circuits - Other Types | PHASE DETECTOR |
JESD-30 code | R-PDIP-T16 |
length | 20.32 mm |
Number of functions | 1 |
Number of terminals | 16 |
Maximum operating temperature | 70 °C |
Minimum operating temperature | |
Package body material | PLASTIC/EPOXY |
encapsulated code | DIP |
Package shape | RECTANGULAR |
Package form | IN-LINE |
Maximum seat height | 4.58 mm |
Maximum supply voltage (Vsup) | 5.5 V |
Minimum supply voltage (Vsup) | 4.5 V |
Nominal supply voltage (Vsup) | 5 V |
surface mount | NO |
Temperature level | COMMERCIAL |
Terminal form | THROUGH-HOLE |
Terminal pitch | 2.54 mm |
Terminal location | DUAL |
width | 7.62 mm |