5 V Low Power
EIA RS-485 Transceiver
ADM485
FEATURES
Meets EIA RS-485 standard
5 Mbps data rate
Single 5 V supply
–7 V to +12 V bus common-mode range
High speed, low power BiCMOS
Thermal shutdown protection
Short-circuit protection
Driver propagation delay: 10 ns typical
Receiver propagation delay: 15 ns typical
High-Z outputs with power off
Superior upgrade for LTC485
FUNCTIONAL BLOCK DIAGRAM
ADM485
RO
1
RE
2
DE
3
DI
4
D
R
8
V
CC
B
A
GND
00078-001
7
6
5
Figure 1.
APPLICATIONS
Low power RS-485 systems
DTE/DCE interface
Packet switching
Local area networks (LNAs)
Data concentration
Data multiplexers
Integrated services digital network (ISDN)
GENERAL DESCRIPTION
The ADM485 is a differential line transceiver suitable for high
speed bidirectional data communication on multipoint bus
transmission lines. It is designed for balanced data transmission
and complies with EIA standards RS-485 and RS-422. The part
contains a differential line driver and a differential line receiver.
Both the driver and the receiver can be enabled independently.
When disabled, the outputs are three-stated.
The ADM485 operates from a single 5 V power supply.
Excessive power dissipation caused by bus contention or by
output shorting is prevented by a thermal shutdown circuit. If
during fault conditions, a significant temperature increase is
detected in the internal driver circuitry, this feature forces the
driver output into a high impedance state.
Up to 32 transceivers can be connected simultaneously on a
bus, but only one driver should be enabled at any time. It is
important, therefore, that the remaining disabled drivers do not
load the bus. To ensure this, the ADM485 driver features high
output impedance when disabled and when powered down,
which minimizes the loading effect when the transceiver is not
being used. The high impedance driver output is maintained
over the common-mode voltage range of −7 V to +12 V.
Rev. F
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
The receiver contains a fail-safe feature that results in a logic
high output state if the inputs are unconnected (floating).
The ADM485 is fabricated on BiCMOS, an advanced mixed
technology process combining low power CMOS with fast
switching bipolar technology. All inputs and outputs contain
protection against ESD; all driver outputs feature high source
and sink current capability. An epitaxial layer is used to guard
against latch-up.
The ADM485 features extremely fast switching speeds. Minimal
driver propagation delays permit transmission at data rates up
to 5 Mbps while low skew minimizes EMI interference.
The part is fully specified over the commercial and industrial
temperature range and is available in 8-lead PDIP, 8-lead SOIC,
and small footprint, 8-lead MSOP packages.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©1993–2008 Analog Devices, Inc. All rights reserved.
ADM485
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Specifications .................................................................. 4
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 7
Test Circuits..................................................................................... 10
Switching Characteristics .............................................................. 11
Applications Information .............................................................. 12
Differential Data Transmission ................................................ 12
Cable and Data Rate................................................................... 12
Thermal Shutdown .................................................................... 12
Propagation Delay ...................................................................... 12
Receiver Open Circuit, Fail-Safe .............................................. 12
Outline Dimensions ....................................................................... 13
Ordering Guide .......................................................................... 14
REVISION HISTORY
04/08—Rev. E to Rev. F
Updated Format..................................................................Universal
Changes to Table 2............................................................................ 4
Updated Outline Dimension......................................................... 13
Changes to Ordering Guide .......................................................... 14
10/03—Rev. D to Rev. E
Changes to Timing Specifications .................................................. 2
Updated Ordering Guide................................................................. 3
7/03—Rev. C to Rev. D
Changes to Absolute Maximum Ratings ....................................... 3
Changes to Ordering Guide ............................................................ 3
Update to Outline Dimensions....................................................... 9
1/03—Rev. B to Rev. C.
Change to Specifications ..................................................................2
Change to Ordering Guide...............................................................3
12/02—Rev. A to Rev. B.
Deleted Q-8 Package ..........................................................Universal
Edits to Features.................................................................................1
Edits to General Description ...........................................................1
Edits, additions to Specifications.....................................................2
Edits, additions to Absolute Maximum Ratings............................3
Additions to Ordering Guide...........................................................3
TPCs Updated and Reformatted .....................................................5
Addition of 8-Lead MSOP Package ................................................9
Update to Outline Dimensions........................................................9
Rev. F | Page 2 of 16
ADM485
SPECIFICATIONS
V
CC
= 5 V ± 5%, all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 1.
Parameter
DRIVER
Differential Output Voltage, V
OD
Min
Typ
Max
5.0
5.0
5.0
5.0
0.2
3
0.2
250
250
0.8
±1.0
−0.2
70
12
1
–0.8
0.8
2.0
±1
0.4
4.0
7
85
±1.0
1.0
0.6
2.2
1
+0.2
Unit
V
V
V
V
V
V
V
mA
mA
V
V
μA
V
mV
kΩ
mA
mA
V
V
μA
V
V
mA
μA
mA
mA
Test Conditions/Comments
R = ∞, see Figure 20
V
CC
= 5 V, R = 50 Ω (RS-422), see Figure 20
R = 27 Ω (RS-485), see Figure 20
V
TST
= −7 V to +12 V, see Figure 21
R = 27 Ω or 50 Ω, see Figure 20
R = 27 Ω or 50 Ω, see Figure 20
R = 27 Ω or 50 Ω
−7 V ≤ V
O
≤ +12 V
−7 V ≤ V
O
≤ +12 V
V
OD3
Δ|V
OD
| for Complementary Output States
Common-Mode Output Voltage, V
OC
Δ|V
OD
| for Complementary Output States
Output Short-Circuit Current, V
OUT
= High
Output Short-Circuit Current, V
OUT
= Low
CMOS Input Logic Threshold Low, V
INL
CMOS Input Logic Threshold High, V
INH
Logic Input Current (DE, DI)
RECEIVER
Differential Input Threshold Voltage, V
TH
Input Voltage Hysteresis, ΔV
TH
Input Resistance
Input Current (A, B)
CMOS Input Logic Threshold Low, V
INL
CMOS Input Logic Threshold High, V
INH
Logic Enable Input Current (RE)
CMOS Output Voltage Low, V
OL
CMOS Output Voltage High, V
OH
Short-Circuit Output Current
Three-State Output Leakage Current
POWER SUPPLY CURRENT
I
CC
, Outputs Enabled
I
CC
, Outputs Disabled
2.0
1.5
1.5
35
35
2.0
−7 V ≤ V
CM
≤ +12 V
V
CM
= 0 V
−7 V ≤ V
CM
≤ +12 V
V
IN
= 12 V
V
IN
= −7 V
I
OUT
= 4.0 mA
I
OUT
= −4.0 mA
V
OUT
= GND or V
CC
0.4 V ≤ V
OUT
≤ 2.4 V
Digital inputs = GND or V
CC
Digital inputs = GND or V
CC
Rev. F | Page 3 of 16
ADM485
TIMING SPECIFICATIONS
V
CC
= 5 V ± 5%, all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 2.
Parameter
DRIVER
Propagation Delay Input to Output, t
PLH
, t
PHL
Driver Output to OUTPUT, t
SKEW
Driver Rise/Fall Time, t
R
, t
F
Driver Enable to Output Valid
Driver Disable Timing
Matched Enable Switching |t
ZH
− t
ZL
|
Matched Disable Switching |t
HZ
− t
LZ
|
RECEIVER
Propagation Delay Input to Output, t
PLH
, t
PHL
Skew |t
PLH
− t
PHL
|
Receiver Enable, t
ZH
, t
ZL
Receiver Disable, t
HZ
, t
LZ
Tx Pulse Width Distortion
Rx Pulse Width Distortion
1
Min
2
Typ
10
1
8
10
10
0
0
15
5
5
1
1
Max
15
5
15
25
25
2
2
30
5
20
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Test Conditions/Comments
R
LDIFF
= 54 Ω, C
L1
= C
L2
= 100 pF, see Figure 22
R
LDIFF
= 54 Ω, C
L1
= C
L2
= 100 pF, see Figure 22
R
LDIFF
= 54 Ω, C
L1
= C
L2
= 100 pF, see Figure 22
R
L
= 110 Ω, C
L
= 50 pF, see Figure 23
R
L
= 110 Ω, C
L
= 50 pF, see Figure 23
R
L
= 110 Ω, C
L
= 50 pF, see Figure 23
1
R
L
= 110 Ω, C
L
= 50 pF, see Figure 23
1
C
L
= 15 pF, see Figure 24
C
L
= 15 pF, see Figure 24
C
L
= 15 pF, R
L
= 1 kΩ, see Figure 25
C
L
= 15 pF, R
L
= 1 kΩ, see Figure 25
8
Guaranteed by characterization.
Rev. F | Page 4 of 16
ADM485
ABSOLUTE MAXIMUM RATINGS
T
A
= 25°C, unless otherwise noted.
Table 3.
Parameter
V
CC
Inputs
Driver Input (DI)
Control Inputs (DE, RE)
Receiver Inputs (A, B)
Outputs
Driver Outputs (A, B)
Receiver Output
Power Dissipation 8-Lead MSOP
θ
JA
, Thermal Impedance
Power Dissipation 8-Lead PDIP
θ
JA
, Thermal Impedance
Power Dissipation 8-Lead SOIC
θ
JA
, Thermal Impedance
Operating Temperature Range
Commercial Range (J Version)
Industrial Range (A Version)
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
Vapor Phase (60 sec)
Infrared (15 sec)
Rating
−0.3 V to +7 V
−0.3 V to V
CC
+ 0.3 V
−0.3 V to V
CC
+ 0.3 V
−9 V to +14 V
−9 V to +14 V
−0.5 V to V
CC
+ 0.5 V
900 mW
206°C/W
500 mW
130°C/W
450 mW
170°C/W
0°C to 70°C
−40°C to +85°C
−65°C to +150°C
300°C
215°C
220°C
Table 4. Transmitting
DE
1
1
0
1
2
Inputs
DI
1
0
X
1
Outputs
B
0
1
Z
2
A
1
0
Z
2
X = don’t care.
Z = high impedance.
Table 5. Receiving
RE
0
0
0
1
1
2
Input A − Input B
≥ +0.2 V
≤ −0.2 V
Inputs open
X
1
Output RO
1
0
1
Z
2
X = don’t care.
Z = high impedance.
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. F | Page 5 of 16
Analogue and Mixed Signal
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