Changes to Ordering Guide .......................................................... 21
Rev. D | Page 2 of 24
AD7887
SPECIFICATIONS
V
DD
= 2.7 V to 5.25 V, V
REF
= 2.5 V, external/internal reference unless otherwise noted, f
SCLK
= 2 MHz, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Table 1.
Parameter
DYNAMIC PERFORMANCE
Signal to Noise + Distortion Ratio (SNR)
2, 3
Total Harmonic Distortion (THD)
2
Peak Harmonic or Spurious Noise
2
Intermodulation Distortion (IMD)
2
Second-Order Terms
Third-Order Terms
Channel-to-Channel Isolation
2
Full-Power Bandwidth
DC ACCURACY
Resolution
Integral Nonlinearity
2
Differential Nonlinearity
2
Offset Error
2
A Version
1
71
−80
–80
−80
−80
−80
2.5
12
±2
±2
±3
±4
±6
0.5
±2
±1
±6
2
0 to V
REF
±5
20
2.5/V
DD
10
2.45/2.55
±50
2.4
2.1
0.8
±1
10
B Version
1
71
−80
−80
−80
−80
−80
2.5
12
±1
±1
±3
±4
±6
0.5
±2
±1
±6
2
0 to V
REF
±5
20
2.5/V
DD
10
2.45/2.55
±50
2.4
2.1
0.8
±1
10
Unit
dB typ
dB typ
dB typ
dB typ
dB typ
dB typ
MHz typ
Bits
LSB max
LSB max
LSB max
LSB max
LSB typ
LSB max
LSB max
LSB max
LSB typ
LSB max
V
μA max
pF typ
V min/max
kΩ typ
V min/max
ppm/°C typ
V min
V min
V max
μA max
pF max
Functional from 1.2 V
Very high impedance if internal reference disabled
Test Conditions/Comments
f
IN
= 10 kHz sine wave, f
SAMPLE
= 125 kSPS
f
IN
= 10 kHz sine wave, f
SAMPLE
= 125 kSPS
f
IN
= 10 kHz sine wave, f
SAMPLE
= 125 kSPS
fa = 9.983 kHz, fb = 10.05 kHz, f
SAMPLE
= 125 kSPS
fa = 9.983 kHz, fb = 10.05 kHz, f
SAMPLE
= 125 kSPS
f
IN
= 25 kHz
@ 3 dB
Any channel
Guaranteed no missing codes to 11 bits (A Grade)
V
DD
= 5 V, dual-channel mode
V
DD
= 3 V, dual-channel mode
Single-channel mode
Dual-channel mode
Single-channel mode, external reference
Single-channel mode, internal reference
Offset Error Match
2
Gain Error
2
Gain Error Match
2
ANALOG INPUT
Input Voltage Ranges
Leakage Current
Input Capacitance
REFERENCE INPUT/OUTPUT
REF
IN
Input Voltage Range
Input Impedance
REF
OUT
Output Voltage
REF
OUT
Temperature Coefficient
LOGIC INPUTS
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current, I
IN
Input Capacitance, C
IN 4
LOGIC OUTPUTS
Output High Voltage, V
OH
Output Low Voltage, V
OL
Floating-State Leakage Current
Floating-State Output Capacitance
5
Output Coding
V
DD
= 4.75 V to 5.25 V
V
DD
= 2.7 V to 3.6 V
V
DD
= 2.7 V to 5.25 V
Typically 10 nA, V
IN
= 0 V or V
DD
V
DD
− 0.5
V
DD
− 0.5
0.4
0.4
±1
±1
10
10
Straight (Natural) Binary
V min
V max
μA max
pF max
I
SOURCE
= 200 μA
V
DD
= 2.7 V to 5.25 V
I
SINK
= 200 μA
Rev. D | Page 3 of 24
AD7887
Parameter
CONVERSION RATE
Throughput Time
Track/Hold Acquisition Time
2
Conversion Time
POWER REQUIREMENTS
V
DD
I
DD
Normal Mode
5
(Mode 2)
Static
Operational (f
SAMPLE
= 125 kSPS)
Using Standby Mode (Mode 4)
Using Shutdown Mode (Modes 1, 3)
Standby Mode
6
Shutdown Mode
6
Normal Mode Power Dissipation
Shutdown Power Dissipation
Standby Power Dissipation
A Version
1
16
1.5
14.5
+2.7/+5.25
B Version
1
16
1.5
14.5
+2.7/+5.25
Unit
SCLK cycles
SCLK cycles
SCLK cycles
V min/max
Test Conditions/Comments
Conversion time plus acquisition time is 125 kSPS,
with 2 MHz Clock
7.25 μs (2 MHz Clock)
700
850
700
450
120
12
210
1
2
3.5
2.1
5
3
1.05
630
700
850
700
450
120
12
210
1
2
3.5
2.1
5
3
1.05
630
μA max
μA typ
μA typ
μA typ
μA typ
μA typ
μA max
μA max
μA max
mW max
mW max
μW max
μW max
mW max
μW max
Internal reference enabled
Internal reference disabled
f
SAMPLE
= 50 kSPS
f
SAMPLE
= 10 kSPS
f
SAMPLE
= 1 kSPS
V
DD
= 2.7 V to 5.25 V
V
DD
= 2.7 V to 3.6 V
V
DD
= 4.75 V to 5.25 V
V
DD
= 5 V
V
DD
= 3 V
V
DD
= 5 V
V
DD
= 3 V
V
DD
= 5 V
V
DD
= 3 V
1
2
Temperature range for A and B versions is −40°C to +125°C.
See the Terminology section.
3
SNR calculation includes distortion and noise components.
4
Sample tested at +25°C to ensure compliance.
5
All digital inputs at GND except CS at V
DD
. No load on the digital outputs. Analog inputs at GND.
6
SCLK at GND when SCLK off. All digital inputs at GND except for CS at V
DD
. No load on the digital outputs. Analog inputs at GND.
Rev. D | Page 4 of 24
AD7887
TIMING SPECIFICATIONS
1
Table 2.
Limit at T
MIN
, T
MAX
(A, B Versions)
4.75 V to 5.25 V
2.7 V to 3.6 V
2
2
14.5 × t
SCLK
14.5 × t
SCLK
1.5 × t
SCLK
1.5 × t
SCLK
10
10
30
60
75
100
20
20
20
20
0.4 × t
SCLK
0.4 × t
SCLK
0.4 × t
SCLK
0.4 × t
SCLK
80
80
5
5
Parameter
f
SCLK 2
t
CONVERT
t
ACQ
t
1
t
2 3
t
33
t
4
t
5
t
6
t
7
t
8 4
t
9
1
2
Unit
MHz max
Description
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns max
μs typ
Throughput time = t
CONVERT
+ t
ACQ
= 16 t
SCLK
CS to SCLK setup time
Delay from CS until DOUT three-state disabled
Data access time after SCLK falling edge
Data setup time prior to SCLK rising edge
Data valid to SCLK hold time
SCLK high pulse width
SCLK low pulse width
CS rising edge to DOUT high impedance
Power-up time from shutdown
Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6 V.
Mark/space ratio for the SCLK input is 40/60 to 60/40.
3
Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.0 V.
4
t
8
is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
8
, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
200µA
I
OL
TO
OUTPUT
PIN
1.6V
C
L
50pF
200µA
I
OH
06191-002
Figure 2. Load Circuit for Digital Output Timing Specifications
京公网安备 11010802033920号
EEWORLD
