liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause
failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written
assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. 00D
02/27/2013
1
IS61(64)NLP102436B/IS61(64)NVP/NVVP102436B
IS61(64)NLP204818B/IS61(64)NVP/NVVP204818B
BLOCK DIAGRAM
A0-20 ( A0-21)
A0-20(A0-21)
Address
Registers
MODE
ADV
A0-A1
K
CLK
Address
Registers
Burst Logic
K
A'0-A'1
A2-20(A2-A21)
A0-20 ( A0-21)
1Mx36;
2Mx18
Memory Array
Address
Registers
/CKE
Data-In
Register
K
Control register
/CE
CE2
/CE2
ADV
/WE
/BWx
(X=a,b,c,d or a,b)
Data-In
Register
Control Logic
K
/OE
ZZ
36(18)
DQx/DQPx
K
Output
Buffers
Output
Register
K
2
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00D
02/27/2013
IS61(64)NLP102436B/IS61(64)NVP/NVVP102436B
IS61(64)NLP204818B/IS61(64)NVP/NVVP204818B
119-PIN BGA
119-Ball, 14x22 mm BGA
165-PIN BGA
165-Ball, 13x15 mm BGA
Bottom View
Bottom View
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00D
02/27/2013
3
IS61(64)NLP102436B/IS61(64)NVP/NVVP102436B
IS61(64)NLP204818B/IS61(64)NVP/NVVP204818B
PIN CONFIGURATION — 1M
x
36, 165-Ball PBGA (TOP VIEW)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
NC
NC
DQPc
DQc
DQc
DQc
DQc
NC
DQd
DQd
DQd
DQd
DQPd
NC
MODE
2
A
A
NC
DQc
DQc
DQc
DQc
NC
DQd
DQd
DQd
DQd
NC
NC
A
3
CE
CE2
V
ddq
V
ddq
V
ddq
V
ddq
V
ddq
NC
V
ddq
V
ddq
V
ddq
V
ddq
V
ddq
A
A
4
BWc
BWd
V
SS
V
dd
V
dd
V
dd
V
dd
V
dd
V
dd
V
dd
V
dd
V
dd
V
SS
A
A
5
BWb
BWa
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TdI
TMS
6
CE2
CLK
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
A1*
A0*
7
CKE
WE
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDO
TCK
8
ADV
OE
V
SS
V
dd
V
dd
V
dd
V
dd
V
dd
V
dd
V
dd
V
dd
V
dd
V
SS
A
A
9
A
A
V
ddq
V
ddq
V
ddq
V
ddq
V
ddq
NC
V
ddq
V
ddq
V
ddq
V
ddq
V
ddq
A
A
10
A
A
NC
DQb
DQb
DQb
DQb
NC
DQa
DQa
DQa
DQa
NC
A
A
11
NC
NC
DQPb
DQb
DQb
DQb
DQb
ZZ
DQa
DQa
DQa
DQa
DQPa
NC
A
Note:
A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
A
A0, A1
ADV
Pin Name
Synchronous Address Inputs
Synchronous Burst Address Inputs
Synchronous Burst Address Advance/
Load
WE
Synchronous Read/Write Control Input
CLK
Synchronous Clock
CKE
Synchronous Clock Enable
CE, CE2,
CE2 Synchronous Chip Enable
BWa-BWd
Synchronous Byte Write Inputs
OE
Asynchronous Output Enable
ZZ
Asynchronous Power Sleep
Mode
MODE
TCK, TDI
TDO, TMS
V
DD
NC
DQa-DQd
DQPa-DQPd
V
DDQ
V
SS
Burst Sequence Selection
JTAG Pins
Power Supply
No Connect
Synchronous Data Inputs/Outputs
Synchronous Parity Data
Inputs/Outputs
I/O Power Supply
Ground
4
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00D
02/27/2013
IS61(64)NLP102436B/IS61(64)NVP/NVVP102436B
IS61(64)NLP204818B/IS61(64)NVP/NVVP204818B
119-PIN
PBGA PACKAGE
CONFIGURATION
1
2
3
1M x 36 (TOP VIEW)
4
5
6
7
A
B
C
D
E
F
V
DDQ
NC
NC
DQc
DQc
V
DDQ
DQc
DQc
V
DDQ
DQd
DQd
V
DDQ
DQd
DQd
NC
NC
V
DDQ
A
CE2
A
DQPc
DQc
DQc
DQc
DQc
V
DD
DQd
DQd
DQd
DQd
DQPd
A
NC
TMS
A
A
A
V
SS
V
SS
V
SS
BWc
V
SS
NC
V
SS
BWd
V
SS
V
SS
V
SS
MODE
A
TDI
A
ADV
V
DD
NC
CE
OE
A
WE
V
DD
CLK
NC
CKE
A
1
*
A
0
*
V
DD
A
TCK
A
A
A
Vss
Vss
Vss
BWb
Vss
NC
Vss
BWa
Vss
Vss
Vss
NC
A
TDO
A
CE2
A
DQPb
DQb
DQb
DQb
DQb
V
DD
DQa
DQa
DQa
DQa
DQPa
A
A
NC
V
DDQ
NC
NC
DQb
DQb
V
DDQ
DQb
DQb
V
DDQ
DQa
DQa
V
DDQ
DQa
DQa
NC
ZZ
V
DDQ
G
H
J
K
L
M
N
P
R
T
U
Note:
A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
京公网安备 11010802033920号
EEWORLD
