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QL24X32B-0CG68M883C

Description
Military 5.0V pASIC 1 Family - Very-High-Speed CMOS FPGA
File Size318KB,16 Pages
ManufacturerETC1
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QL24X32B-0CG68M883C Overview

Military 5.0V pASIC 1 Family - Very-High-Speed CMOS FPGA

Military 5.0V pASIC 1 Family
Military 5.0V pASIC 1 Family - Very-High-Speed CMOS FPGA
Military 5.0V pASIC 1 Family
D
EVICE
H
IGHLIGHTS
Device Highlights
Features
s
F
EATURES
Total of 180 I/O pins
s
s
s
Very High Speed
s
ViaLink“ metal-to-metal programmable technol-
ogy, allows counter speeds over 150 MHz and
logic cell delays of under 2 ns at 5V, and over 80
MHz at 3.3V operation.
-172 Bidirectional Input/Output pins
-6 Dedicated Input/High-Drive pins
-2 Clock/Dedicated input pins with fanout-
independent, low-skew clock networks
-PCI 2.1 Compliant I/Os
High Usable Density
s
s
s
s
s
Up to a 24-by-32 array of 768 logic cells provides
22,000 usable PLD gates in 208-pin PQFP and
208-pin CQFP packages.
Input + logic cell + output delays under 6 ns
Chip-to-chip operating frequencies up to 110 MHz
Internal state machine frequencies up to 150 MHz
Clock skew < 0.5 ns
Input hysteresis provides high noise immunity
Built-in scan path permits 100% factory testing of
logic and I/O cells and functional testing with Auto-
matic Test Vector Generation (ATVG) software
after programming
208 pin PQFP pin for pin compatible with the
208 CQFP
0.65µ CMOS process with ViaLink programming
technology
PCI-Output Drive
s
s
s
s
Fully PCI 2.1 compliant input/output capability.
(including drive current)
s
s
Device
ASIC
Gates
PLD
Gates
Package
Max
I/O
Qualification
Level
SMD
5962-
QL8x12B
QL12x16B
QL16x24B
QL24x32B
1,000
2,000
4,000
8,000
2,000
4,000
7,000
14,000
68CPGA
84CPGA
144CPGA
160 CQFP
208CQFP
208PQFP
64
76
122
122
180
180
M
M, /883
M, /883
M, /883
M, /883
M
96836
95599
95599
96837
M = Military Temperature (-55 to +125 degrees C)
/883 = MIL-STD-883 qualified
TABLE 1: Selector Table
Rev B
8-7

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Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
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