W989D2CKGX7G datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > W989D2CKGX7G

Preview

W989D2CKGX7G: Description512Mb Mobile LPSDR; File Size1MB，65 Pages; ManufacturerWinbond Electronics Corporation; Websitehttp://www.winbond.com.tw

Download Datasheet View All

W989D2CKGX7G Overview

512Mb Mobile LPSDR

Preview

Download Datasheet

View All

W989D6CB / W989D2CB

512Mb Mobile LPSDR

1. GENERAL DESCRIPTION

The Winbond 512Mb Low Power SDRAM is a low power synchronous memory containing

536,870,912 memory cells fabricated with Winbond high performance process technology.

It is designed to consume less power than the ordinary SDRAM with low power features essential

for applications which use batteries. It is available in two organizations: 4,194,304-words × 4 banks

× 32 bits or 8,388,608 words × 4 banks × 16 bits. The device operates in a fully synchronous

mode, and the output data are synchronized to positive edges of the system clock and is capable

of delivering data at clock rate up to 166MHz. The device supports special low power functions

such as Partial Array Self Refresh (PASR) and Automatic Temperature Compensated Self Refresh

(ATCSR).

The Low Power SDRAM is suitable for 2.5G / 3G cellular phone, PDA, digital still camera, mobile

game consoles and other handheld applications where large memory density and low power

consumption are required. The device operates from 1.8V power supply, and supports the 1.8V

LVCMOS bus interface.

2. FEATURES



Power supply V

= 1.7V~1.95V



DDQ

= 1.7V~1.95V



Frequency : 166MHz(-6),133MHz(-75)



Programmable Partial Array Self Refresh



Power Down Mode



Deep Power Down Mode (DPD)



Programmable output buffer driver strength



Automatic Temperature Compensated Self Refresh



CAS

Latency: 2 and 3



Burst Length: 1, 2, 4, 8, and full page



Refresh: refresh cycle 64ms



Interface: LVCMOS



Support package :

54 balls VFBGA (x16)

90 balls VFBGA (x32)



Operating Temperature Range

Extended (-25°C ~ +85°C)

Industrial (-40°C ~ +85°C)

- 1 -

Publication Release Date : August 07, 2013

Revision : A01-006

W989D6CB / W989D2CB

512Mb Mobile LPSDR

TABLE OF CONTENTS

1. GENERAL DESCRIPTION .......................................................................................................... 1

2. FEATURES .................................................................................................................................. 1

3.ORDERING INFORMATION ........................................................................................................ 2

4. PIN CONFIGURATION ................................................................................................................ 5

4.1 Ball Assignment: LPSDR X 16 ............................................................................................................ 5

4.2 Ball Assignment: LPSDR X 32 ............................................................................................................ 5

5. PIN DESCRIPTION...................................................................................................................... 6

5.1 Signal Description ............................................................................................................................... 6

5.2 Addressing Table ................................................................................................................................ 6

6. BLOCK DIAGRAM ...................................................................................................................... 7

7. ELECTRICAL CHARACTERISTICS ........................................................................................... 8

7.1 Absolute Maximum Ratings ................................................................................................................ 8

7.2 Operating Conditions .......................................................................................................................... 8

7.3 Capacitance ........................................................................................................................................ 8

7.4 DC Characteristics .............................................................................................................................. 9

7.5 Automatic Temperature Compensated Self Refresh Current Feature .............................................. 11

7.6 AC Characteristics And AC Operating Conditions ............................................................................ 12

7.6.1 AC Characteristics.................................................................................................................................... 12

7.6.2 AC Test Condition .................................................................................................................................... 13

7.6.3 AC Latency Characteristics ...................................................................................................................... 14

8. FUNCTION DESCRIPTION ....................................................................................................... 15

8.1 Command Function ........................................................................................................................... 15

8.1.1Table 1. Truth Table .................................................................................................................................. 15

8.1.2 Functional Truth Table ............................................................................................................................. 16

8.1.3 Function Truth Table for CKE .................................................................................................................. 19

8.1.4 Bank Activate Command .......................................................................................................................... 20

8.1.5 Bank Precharge Command ...................................................................................................................... 20

8.1.6 Precharge All Command .......................................................................................................................... 20

8.1.7 Write Command ....................................................................................................................................... 20

8.1.8 Write with Auto Precharge Command ...................................................................................................... 20

8.1.9 Read Command ....................................................................................................................................... 20

8.1.10 Read with Auto Precharge Command.................................................................................................... 20

8.1.11 Extended Mode Register Set Command ............................................................................................... 20

8.1.12 Mode Register Set Command ................................................................................................................ 21

8.1.13 No-Operation Command ........................................................................................................................ 21

8.1.14 Burst Stop Command ............................................................................................................................. 21

8.1.15 Device Deselect Command.................................................................................................................... 21

8.1.16 Auto Refresh Command ......................................................................................................................... 21

8.1.17 Self Refresh Entry Command ................................................................................................................ 21

8.1.18 Self Refresh Exit Command ................................................................................................................... 21

8.1.19 Clock Suspend Mode Entry/Power Down Mode Entry Command ......................................................... 21

8.1.20 Clock Suspend Mode Exit / Power Down Mode Exit Command ............................................................ 21

8.1.21 Data Write/Output Enable, Data Mask/Output Disable Command ........................................................ 22

9.OPERATION ............................................................................................................................... 22

9.1 Read Operation ................................................................................................................................. 22

9.2 Write Operation ................................................................................................................................. 22

9.3 Precharge ......................................................................................................................................... 23

9.3.1 Auto Precharge ........................................................................................................................................ 23

9.3.2 READ with auto precharge interrupted by a READ (with or without auto precharge) ............................. 23

9.3.3 READ with auto precharge interrupted by a WRITE (with or without auto precharge) ............................ 24

9.3.4 WRITE with auto precharge interrupted by a READ (with or without auto precharge) ............................ 24

- 3 -

Publication Release Date : August 07, 2013

Revision : A01-006

W989D6CB / W989D2CB

512Mb Mobile LPSDR

9.3.5 WRITE with auto precharge interrupted by a WRITE (with or without auto precharge) .......................... 25

9.4 Burst Termination .............................................................................................................................. 25

9.5 Mode Register Operation .................................................................................................................. 26

9.5.1 Burst Length field (A2~A0) ....................................................................................................................... 26

9.5.2 Addressing Mode Select (A3) .................................................................................................................. 26

9.5.3 Addressing Sequence for Sequential Mode ............................................................................................. 27

9.5.4 Addressing Sequence for Interleave Mode .............................................................................................. 27

9.5.5 Addressing Sequence Example (Burst Length = 8 and Input Address is 13) .......................................... 28

9.5.6 Read Cycle

CAS

Latency = 3 ................................................................................................................ 28

9.5.7

CAS

Latency field (A6~A4).................................................................................................................... 29

9.5.8 Mode Register Definition .......................................................................................................................... 29

9.6 Extended Mode Register Description................................................................................................ 30

9.7 Simplified State Diagram................................................................................................................... 31

10. CONTROL TIMING WAVEFORMS ......................................................................................... 32

10.1 Command Input Timing ................................................................................................................... 32

10.2 Read Timing .................................................................................................................................... 33

10.3 Control Timing of Input Data (x16) .................................................................................................. 34

10.4 Control Timing of Output Data (x16) ............................................................................................... 35

10.5 Control Timing of Input Data (x32) .................................................................................................. 36

10.6 Control Timing of Output Data (x32) ............................................................................................... 37

10.7 Mode register Set (MRS) Cycle ...................................................................................................... 38

10.8 Extended Mode register Set (EMRS) Cycle .................................................................................... 39

11. OPERATING TIMING EXAMPLE ............................................................................................ 40

11.1 Interleaved Bank Read (Burst Length = 4,

CAS

Latency = 3) ....................................................... 40

11.2 Interleaved Bank Read (Burst Length = 4,

CAS

Latency = 3, Auto Precharge) ............................ 41

11.3 Interleaved Bank Read (Burst Length = 8,

CAS

Latency = 3) ....................................................... 42

11.4 Interleaved Bank Read (Burst Length = 8,

CAS

Latency = 3, Auto Precharge) ............................ 43

11.5 Interleaved Bank Write (Burst Length = 8) ...................................................................................... 44

11.6 Interleaved Bank Write (Burst Length = 8, Auto Precharge) ........................................................... 45

11.7 Page Mode Read (Burst Length = 4,

CAS

Latency = 3) ............................................................... 46

11.8 Page Mode Read / Write (Burst Length = 8,

CAS

Latency = 3) .................................................... 47

11.9 Auto Precharge Read (Burst Length = 4,

CAS

Latency = 3) ......................................................... 48

11.10 Auto Precharge Write (Burst Length = 4) ...................................................................................... 49

11.11 Auto Refresh Cycle ....................................................................................................................... 50

11.12 Self Refresh Cycle ........................................................................................................................ 51

11.13 Power Down Mode ........................................................................................................................ 52

11.14 Burst Read and Single Write (Burst Length = 4,

CAS

Latency = 3) ............................................ 53

11.15 Deep Power Down Mode Entry ..................................................................................................... 54

11.16 Deep Power Down Mode Exit ....................................................................................................... 55

11.17 Auto Precharge Timing (Read Cycle) ........................................................................................... 56

11.18 Auto Precharge Timing (Write Cycle)............................................................................................ 57

11.19 Timing Chart of Read to Write Cycle............................................................................................. 58

11.20 Timing Chart for Write to Read Cycle ........................................................................................... 58

11.21 Timing Chart for Burst Stop Cycle (Burst Stop Command) ........................................................... 59

11.22 Timing Chart for Burst Stop Cycle (Precharge Command) ........................................................... 59

11.23 CKE/DQM Input Timing (Write Cycle) ........................................................................................... 60

11.24 CKE/DQM Input Timing (Read Cycle)........................................................................................... 61

12. PACKAGE DIMENSION .......................................................................................................... 62

12.1 : LPSDR X 16 .................................................................................................................................. 62

12.2 : LPSDR X 32 .................................................................................................................................. 63

13. REVISION HISTORY ............................................................................................................... 64

- 4 -

Publication Release Date : August 07, 2013

Revision : A01-006

Recommended Resources

Crystal oscillator circuit c composed of several gate circuits

5V/10A 20kHz blocking AC converter using SIPMOS transistors

LED-parallel LED digital tube dynamic scanning display circuit (common cathode)

Logic-controlled integrated regulated power supply composed of CW200

Precise second pulse signal generator

transistor proximity switch

Shortcut: 00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

Popular Components