RWR84N3091BPRSL datasheet, PDF

RWR84N3091BPRSL: DescriptionRESISTOR, WIRE WOUND, 7 W, 0.1 %, 20 ppm, 3090 ohm, THROUGH HOLE MOUNT, AXIAL LEADED; CategoryPassive components The resistor; File Size158KB，3 Pages; ManufacturerVishay; Websitehttp://www.vishay.com

Download Datasheet Parametric View All

RWR84N3091BPRSL Overview

RESISTOR, WIRE WOUND, 7 W, 0.1 %, 20 ppm, 3090 ohm, THROUGH HOLE MOUNT, AXIAL LEADED

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Vishay
package instruction	Axial,
Reach Compliance Code	compliant
ECCN code	EAR99
Other features	NON INDUCTIVE
structure	Tubular
JESD-609 code	e0
Lead diameter	1.02 mm
Lead length	38.1 mm
Installation features	THROUGH HOLE MOUNT
Number of terminals	2
Maximum operating temperature	250 °C
Minimum operating temperature	-55 °C
Package diameter	7.92 mm
Package length	22.23 mm
Package form	Axial
method of packing	TR
Rated power dissipation(P)	7 W
Rated temperature	25 °C
Guideline	MIL-PRF-39007
resistance	3090 Ω
Resistor type	FIXED RESISTOR
surface mount	NO
technology	WIRE WOUND
Temperature Coefficient	20 ppm/°C
Terminal surface	Tin/Lead (Sn60Pb40)
Terminal shape	WIRE
Tolerance	0.1%
Operating Voltage	147.0714 V

Weekly highlights: 2018.10.22-10.28: [size=4]Hi, good afternoon everyone~~ It's time for another weekly review. Today's review is a little late~ Please forgive me~~ [b][color=#ff0000]Review of wonderful posts:[/color][/b][/size][size=4][...; okhxyyo Talking

bluenrg-2 cannot connect to other devices directly when it is the host: After successful initialization, the function aci_gap_create_connection is used to connect directly according to the address, but it returns 0x46 BLE_STATUS_NOT_ALLOWED. The connection cannot be succe...; 拱墅区第一渣男小面包 ST - Low Power RF

Using STM32's MPU (Memory Protection Unit) to implement code isolation and access control: Problem/Goal and SolutionObjective: Only allow "high-level functions" to access data in OTP, other applications cannot directly read OTP contentExample @ F413-Nucleo, F401-NucleoTarget environmentThe ...; nmg stm32/stm8

FPGA embedded system design.part1.rar: FPGA embedded system design.part1.rar...; zxopenljx EE_FPGA Learning Park

Patents are born from innovation: [i=s]This post was last edited by jameswangsynnex on 2015-3-3 19:59[/i] People often breed fish and shrimps, which often die in large numbers due to water pollution. Even the fish tanks at home need t...; lorant Mobile and portable

Playing with Zynq Serial 43——[ex62] Image Laplace Edge Extraction of OV5640 Camera: 1 System Overview As shown in the figure, this is the principle block diagram of the entire video acquisition system. At the beginning of power-on, the FPGA needs to initialize the register configurat...; ove学习使我快乐 FPGA/CPLD

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components