SPT7861
10-BIT, 40 MSPS, 160 mW A/D CONVERTER
TECHNICAL DATA
JUNE 25, 2001
FEATURES
•
•
•
•
•
•
•
•
•
•
Monolithic 40 MSPS converter
160 mW power dissipation
On-chip track-and-hold
Single +5 V power supply
TTL/CMOS outputs
5 pF input capacitance
Low cost
Tri-state output buffers
High ESD protection: 3,500 V minimum
Selectable +3 V or +5 V logic I/O
APPLICATIONS
• All high-speed applications where low power
dissipation is required
• Video imaging
• Medical imaging
• Radar receivers
• IR imaging
• Digital communications
GENERAL DESCRIPTION
The SPT7861 is a 10-bit monolithic, low-cost, ultralow-
power analog-to-digital converter capable of minimum
word rates of 40 MSPS. This is a pin-compatible improved
version of the SPT7860. The on-chip track-and-hold func-
tion assures excellent dynamic performance without the
need for external components. The input drive require-
ments are minimized due to the SPT7861’s low input
capacitance of only 5 pF.
Power dissipation is extremely low at only 160 mW typical
at 40 MSPS with a power supply of +5.0 V. The digital out-
puts are +3 V or +5 V, and are user selectable. The
SPT7861 is pin-compatible with an entire family of 10-bit,
CMOS converters (SPT7835/40/50/55/60/61), which sim-
plifies upgrades. The SPT7861 has incorporated propri-
etary circuit design and CMOS processing technologies to
achieve its advanced performance. Inputs and outputs are
TTL/CMOS-compatible to interface with TTL/CMOS logic
systems. Output data format is straight binary.
The SPT7861 is available in 28-lead SOIC and 32-lead
small (7 mm square) TQFP packages over the commer-
cial temperature range.
BLOCK DIAGRAM
ADC Section 1
A
IN
1:16
Mux
T/H
Auto-
Zero
CMP
11-Bit
SAR
11
11
D10 Overrange
D9 (MSB)
D8
D7
D6
D5
D4
D3
D2
D1
P1
DAC
CLK In
Timing
and
Control
Enable
.
.
.
P15
P2
P16
.
.
.
ADC Section 15
ADC Section 2
ADC Section 16
T/H
Auto-
Zero
CMP
.
.
.
11-Bit
SAR
11
DAC
11
.
.
.
11
11
11-Bit
16:1
Mux/
Error
Correction
Data
Valid
Ref
In
Reference Ladder
D0 (LSB)
V
REF
ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)
1
25 °C
Supply Voltages
AV
DD
...................................................................... +6 V
DV
DD
..................................................................... +6 V
Input Voltages
Analog Input .............................. –0.5 V to AV
DD
+0.5 V
V
REF
.............................................................. 0 to AV
DD
CLK Input ............................................................... V
DD
AV
DD
– DV
DD
.................................................. ±100 mV
AGND – DGND .............................................. ±100 mV
Output
Digital Outputs ................................................... 10 mA
Temperature
Operating Temperature ................................ 0 to 70 °C
Junction Temperature ........................................ 175 °C
Lead Temperature, (soldering 10 seconds) ....... 300 °C
Storage Temperature ............................ –65 to +150 °C
Note:
1. Operation at any Absolute Maximum Rating is not implied. See
Electrical Specifications for proper nominal applied conditions
in typical applications.
ELECTRICAL SPECIFICATIONS
T
A
=T
MIN
to T
MAX
, AV
DD
=DV
DD
=OV
DD
=+5.0 V, V
IN
=0 to 4 V, ƒ
S
=40 MSPS, V
RHS
=4.0 V, V
RLS
=0.0 V, unless otherwise specified.
PARAMETERS
Resolution
DC Accuracy
Integral Linearity Error (ILE)
Differential Linearity Error (DLE)
No Missing Codes
Analog Input
Input Voltage Range
Input Resistance
Input Capacitance
Input Bandwidth
Offset
Gain Error
Reference Input
Resistance
Bandwidth
Voltage Range
V
RLS
V
RHS
V
RHS
– V
RLS
∆(V
RHF
– V
RHS
)
∆(V
RLS
– V
RLF
)
Reference Settling Time
V
RHS
V
RLS
Conversion Characteristics
Maximum Conversion Rate
Minimum Conversion Rate
Pipeline Delay (Latency)
Aperture Delay Time
Aperture Jitter Time
Dynamic Performance
Effective Number of Bits (ENOB)
ƒ
IN
= 3.58 MHz
ƒ
IN
= 10.3 MHz
Signal-to-Noise Ratio (SNR)
(without Harmonics)
ƒ
IN
= 3.58 MHz
ƒ
IN
= 10.3 MHz
TEST
CONDITIONS
TEST
LEVEL
MIN
10
SPT7861
TYP
MAX
UNITS
Bits
VI
VI
VI
VI
IV
V
V
V
V
VI
V
IV
IV
V
V
V
V
V
VI
IV
IV
V
V
40
2
V
RLS
50
±1.0
±0.5
Guaranteed
V
RHS
5.0
250
±2.0
±2.0
200
100
0
3.0
1.0
400
150
600
2.0
AV
DD
5.0
LSB
LSB
(Small Signal)
V
kΩ
pF
MHz
LSB
LSB
Ω
MHz
V
V
V
mV
mV
Clock Cycles
Clock Cycles
MHz
MHz
Clock Cycles
ns
ps (p-p)
4.0
90
75
15
20
12
4.0
15
VI
VI
VI
VI
56
55
9.2
8.8
58
57
Bits
Bits
dB
dB
SPT7861
2
6/25/01
ELECTRICAL SPECIFICATIONS
T
A
=T
MIN
to T
MAX
, AV
DD
=DV
DD
=OV
DD
=+5.0 V, V
IN
=0 to 4 V, ƒ
S
=40 MSPS, V
RHS
=4.0 V, V
RLS
=0.0 V, unless otherwise specified.
PARAMETERS
Dynamic Performance
Total Harmonic Distortion (THD)
ƒ
IN
= 3.58 MHz
ƒ
IN
= 10.3 MHz
Signal-to-Noise and Distortion
(SINAD)
ƒ
IN
= 3.58 MHz
ƒ
IN
= 10.3 MHz
Spurious Free Dynamic Range
Differential Phase
Differential Gain
Inputs
Logic 1 Voltage
Logic 0 Voltage
Maximum Input Current Low
Maximum Input Current High
Input Capacitance
Digital Outputs
Logic 1 Voltage
Logic 0 Voltage
t
RISE
t
FALL
Output Enable to Data Output Delay
Power Supply Requirements
Voltages
OV
DD
DV
DD
AV
DD
Currents
AI
DD
DI
DD
Power Dissipation
TEST
CONDITIONS
9 Distortion bins from
1024 pt FFT
TEST
LEVEL
MIN
SPT7861
TYP
MAX
UNITS
VI
VI
VI
VI
V
V
V
VI
VI
VI
VI
VI
61
56
54
53
63
58
57
55
64
±0.3
±0.3
dB
dB
dB
dB
dB
Degree
%
V
V
µA
µA
pF
V
V
ns
ns
ns
ns
V
V
V
mA
mA
mW
ƒ
IN
= 1 MHz
2.0
–10
–10
+5
3.5
0.4
10
10
10
22
3.0
4.75
4.75
5.0
5.25
5.25
22
23
225
0.8
+10
+10
I
OH
= 0.5 mA
I
OL
= 1.6 mA
15 pF load
15 pF load
20 pF load, T
A
= +25 °C
50 pF load over temp.
VI
VI
V
V
V
V
IV
IV
IV
VI
VI
VI
5.0
5.0
14
18
160
TEST LEVEL CODES
All electrical characteristics are subject to the
following conditions:
All parameters having min/max specifications
are guaranteed. The Test Level column indi-
cates the specific device testing actually per-
formed during production and Quality Assur-
ance inspection. Any blank section in the data
column indicates that the specification is not
tested at the specified condition.
LEVEL
I
II
III
IV
V
VI
TEST PROCEDURE
100% production tested at the specified temperature.
100% production tested at T
A
= +25 °C, and sample tested at the
specified temperatures.
QA sample tested only at the specified temperatures.
Parameter is guaranteed (but not tested) by design and characteri-
zation data.
Parameter is a typical value for information purposes only.
100% production tested at T
A
= +25 °C. Parameter is guaranteed
over specified temperature range.
SPT7861
3
6/25/01
SPECIFICATION DEFINITIONS
APERTURE DELAY
Aperture delay represents the point in time, relative to the
rising edge of the CLOCK input, that the analog input is
sampled.
APERTURE JITTER
The variations in aperture delay for successive samples.
DIFFERENTIAL GAIN (DG)
A signal consisting of a sine wave superimposed on vari-
ous DC levels is applied to the input. Differential gain is the
maximum variation in the sampled sine wave amplitudes
at these DC levels.
DIFFERENTIAL PHASE (DP)
A signal consisting of a sine wave superimposed on vari-
ous DC levels is applied to the input. Differential phase is
the maximum variation in the sampled sine wave phases
at these DC levels.
EFFECTIVE NUMBER OF BITS (ENOB)
SINAD = 6.02N + 1.76, where N is equal to the effective
number of bits.
SINAD – 1.76
N=
6.02
INPUT BANDWIDTH
Small signal (50 mV) bandwidth (3 dB) of analog input
stage.
DIFFERENTIAL LINEARITY ERROR (DLE)
Error in the width of each code from its theoretical value.
(Theoretical = V
FS
/2
N
)
INTEGRAL LINEARITY ERROR (ILE)
Linearity error refers to the deviation of each individual
code (normalized) from a straight line drawn from –FS
through +FS. The deviation is measured from the edge of
each particular code to the true straight line.
OUTPUT DELAY
Time between the clock’s triggering edge and output data
valid.
OVERVOLTAGE RECOVERY TIME
The time required for the ADC to recover to full accuracy
after an analog input signal 125% of full scale is reduced
to 50% of the full-scale value.
SIGNAL-TO-NOISE RATIO (SNR)
The ratio of the fundamental sinusoid power to the total
noise power. Harmonics are excluded.
SIGNAL-TO-NOISE AND DISTORTION (SINAD)
The ratio of the fundamental sinusoid power to the total
noise and distortion power.
TOTAL HARMONIC DISTORTION (THD)
The ratio of the total power of the first 9 harmonics to the
power of the measured sinusoidal signal.
SPURIOUS FREE DYNAMIC RANGE (SFDR)
The ratio of the fundamental sinusoidal amplitude to the
single largest harmonic or spurious signal.
SPT7861
4
6/25/01
Figure 1A – Timing Diagram 1
1
9
11
13
17
5
7
15
3
ANALOG IN
CLOCK IN
SAMPLING
CLOCK
(Internal)
INVALID
VALID
DATA OUTPUT
DATA VALID
1
2
3
4
5
Figure 1B – Timing Diagram 2
t
CLK
t
C
t
CH
CLOCK IN
t
CL
DATA
OUTPUT
Data 0
t
OD
Data 1
Data 2
Data 3
DATA VALID
t
S
t
S
t
CH
t
CL
Table I – Timing Parameters
DESCRIPTION
Conversion Time
Clock Period
Clock High Duty Cycle
Clock Low Duty Cycle
Clock to Output Delay (15 pF Load)
Clock to DAV
PARAMETERS
t
C
t
CLK
t
CH
t
CL
t
OD
t
S
MIN
t
CLK
25
40
40
50
50
17
10
60
60
TYP
MAX
UNITS
ns
ns
%
%
ns
ns
SPT7861
5
6/25/01
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