SiT5186
ADVANCED
AEC-Q100, 1 to 60 MHz, ±0.5 to ±2.5 ppm, Elite Platform™ Super-TCXO
Description
The
SiT5186 is a ±0.5 to ±2.5 ppm MEMS Super-TCXO
Features
that is engineered for best dynamic performance. It is ideal
for high reliability GNSS-based precision positioning and
timing applications.
Leveraging SiTime’s unique DualMEMS™ temperature
sensing and TurboCompensation™ technologies, the
SiT5186 delivers the best dynamic performance for timing
stability in the presence of environmental stressors due to
air flow, temperature perturbation, vibration, shock, and
electromagnetic interference. This device also integrates
multiple on-chip regulators to filter power supply noise,
eliminating the need for a dedicated external LDO.
The SiT5186 offers three device configurations that can be
ordered using
Ordering Codes
for:
Automotive AEC-Q100 qualified
AEC-Q100 Grade 2 temp. range (-40°C to +105°C)
Grade 3 and 4 also available
Any frequency from 1 MHz to 60 MHz in 1 Hz steps
Factory programmable options for low lead times
Best dynamic stability under airflow, thermal shock
±0.5 ppm stability across temperature
±15 ppb/°C typical frequency slope (ΔF/ΔT)
No activity dips or micro jumps
Resistant to shock, vibration and board bending
On-chip regulators eliminate the need for external LDOs
Digital frequency pulling (DCTCXO) via I
2
C
Digital control of output frequency and pull range
Up to
±3200
ppm pull range
Frequency pull resolution down to 5 ppt
2.5V, 2.8V, 3.0V and 3.3V supply voltage
LVCMOS or clipped sinewave output
RoHS and REACH compliant
Pb-free, Halogen-free, Antimony-free
Applications
The SiT5186 can be factory programmed for any
combination of frequency, stability, voltage, and pull range.
Programmability enables designers to optimize clock
configurations while eliminating long lead times and
customization costs associated with quartz devices where
each frequency is custom built.
Refer to
Manufacturing Guideline
for proper reflow profile
and PCB cleaning recommendations to ensure best
performance.
Precision GNSS systems
Block Diagram
5.0 x 3.2 mm
2
Package Pinout
SDA / NC
OE / VC / NC
SCL / NC
NC
GND
1
10
9
VDD
NC
NC
CLK
2
3
8
7
4
5
6
A0 / NC
Figure 1. SiT5186 Block Diagram
Figure 2. Pin Assignments (Top view)
(Refer to
Table 13
for Pin Descriptions)
Rev 0.3
November 15, 2018
www.sitime.com
SiT5186
AEC-Q100, 1 to 60 MHz, ±0.5 to ±2.5 ppm, Elite Platform™ Super-TCXO
Ordering Information
Part
Family
Silicon
Revision
Letter
Package Size
"F": 5.0 x 3.2 mm
2
Pin 1 Function – TCXO mode only
"E": Output Enable
"N": No Connect
TCXO
VCTCXO
DCTCXO
Temperature Range
SiT5 1 8 6 A E - F K - 33E 0 - 19.123456T
SiT5 1 8 6 A E - F K - 33 V T - 19.123456T
SiT5 1 8 6 A E - F KG 33J R - 19.123456T
Packaging
"T": 12mm Tape & Reel, 3ku reel
"Y": 12mm Tape & Reel, 1ku reel
“X”: 12mm Tape & Reel, 250u reel
(blank): bulk
[2]
Frequency
1.000000 to 60.000000 MHz
"C": -20 to 70
°C, AEC-Q100 Grade4
"I": -40 to 85
°C, AEC-Q100 Grade3
"E": -40 to 105
°C, AEC-Q100 Grade2
Output Waveform
"-": LVCMOS
[1]
"C": Clipped Sinewave
Pull Range
– DCTCXO mode only
Frequency Stability
"K": for
±0.5
ppm
"A": for
±1.0
ppm
"D": for
±2.5
ppm
"T":
±6.25
ppm
"R":
±10
ppm
"Q":
±12.5
ppm
"M":
±25
ppm
"B":
±50
ppm
"C":
±80
ppm
"E":
±100
ppm
"F":
±125
ppm
"G": ±150 ppm
"H": ±200 ppm
"X": ±400 ppm
"L": ±600 ppm
"Y": ±800 ppm
"S": ±1200 ppm
"Z": ±1600 ppm
"U": ±3200 ppm
I
2
C Address Mode
– DCTCXO mode only
Values: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F
Set bits 3:0 of device
I
2
C address to the Hex value
of the ordering code. When the
I
2
C address is
factory programmed using these codes, pin
A0 is NC.
Value: G
The
I
2
C address is controlled by A0 pin.
Pin 1 Function – DCTCXO mode only
"I": Output Enable
"J": No Connect, software OE control
Supply Voltage
"25": 2.5 V
±
10%
"28": 2.8 V
±
10%
"30": 3.0 V
±
10%
"33": 3.3 V
±
10%
Notes:
1. “-“ corresponds to the default rise/fall time for LVCMOS output as specified in
Table 1
(Electrical Characteristics). Contact
SiTime
for other rise/fall time options
for best EMI.
2. Bulk is available for sampling only
Rev 0.3
Page 2 of 36
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SiT5186
AEC-Q100, 1 to 60 MHz, ±0.5 to ±2.5 ppm, Elite Platform™ Super-TCXO
TABLE OF CONTENTS
Description ................................................................................................................................................................................... 1
Features....................................................................................................................................................................................... 1
Applications ................................................................................................................................................................................. 1
Block Diagram ............................................................................................................................................................................. 1
5.0 x 3.2 mm
2
Package Pinout..................................................................................................................................................... 1
Ordering Information .................................................................................................................................................................... 2
Electrical Characteristics.............................................................................................................................................................. 4
Device Configurations and Pin-outs ............................................................................................................................................. 9
Pin-out Top Views................................................................................................................................................................. 9
Test Circuit Diagrams for LVCMOS and Clipped Sinewave Outputs ......................................................................................... 10
Waveforms................................................................................................................................................................................. 12
Timing Diagrams ........................................................................................................................................................................ 13
Typical Performance Plots ......................................................................................................................................................... 14
Architecture Overview ................................................................................................................................................................ 16
Frequency Stability ............................................................................................................................................................. 16
Output Frequency and Format............................................................................................................................................ 16
Output Frequency Tuning ................................................................................................................................................... 16
Pin 1 Configuration (OE, VC, or NC) .................................................................................................................................. 17
Device Configurations ................................................................................................................................................................ 17
TCXO Configuration ........................................................................................................................................................... 17
VCTCXO Configuration ...................................................................................................................................................... 18
DCTCXO Configuration ...................................................................................................................................................... 19
VCTCXO-Specific Design Considerations ................................................................................................................................. 20
Linearity .............................................................................................................................................................................. 20
Control Voltage Bandwidth ................................................................................................................................................. 20
FV Characteristic Slope K
V
................................................................................................................................................. 20
Pull Range, Absolute Pull Range ........................................................................................................................................ 21
DCTCXO-Specific Design Considerations ................................................................................................................................. 22
Pull Range and Average Pull Range .................................................................................................................................. 22
Output Frequency ............................................................................................................................................................... 23
I
2
C Control Registers .......................................................................................................................................................... 25
Register Descriptions.......................................................................................................................................................... 25
Register Address: 0x00. Digital Frequency Control Least Significant Word (LSW) ............................................................ 25
Register Address: 0x01. OE Control, Digital Frequency Control Most Significant Word (MSW)......................................... 26
Register Address: 0x02. DIGITAL PULL RANGE CONTROL
[14]
....................................................................................... 27
Serial Interface Configuration Description .......................................................................................................................... 28
Serial Signal Format ........................................................................................................................................................... 28
Parallel Signal Format ........................................................................................................................................................ 29
Parallel Data Format ........................................................................................................................................................... 29
I
2
C Timing Specification ...................................................................................................................................................... 31
I
2
C Device Address Modes ................................................................................................................................................. 32
Schematic Example ............................................................................................................................................................ 33
Dimensions and Patterns ........................................................................................................................................................... 34
Layout Guidelines ...................................................................................................................................................................... 35
Manufacturing Guidelines .......................................................................................................................................................... 35
Rev 0.3
Page 3 of 36
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SiT5186
AEC-Q100, 1 to 60 MHz, ±0.5 to ±2.5 ppm, Elite Platform™ Super-TCXO
Electrical Characteristics
All Min and Max limits are specified over temperature and rated operating voltage with 15 pF output load unless otherwise
stated. Typical values are at 25°C and 3.3V Vdd.
Table 1. Output Characteristics
Parameters
Nominal Output Frequency Range
Operating Temperature Range
Symbol
F_nom
T_use
Min.
1
-20
-40
-40
Initial Tolerance
Supply Voltage Sensitivity
F_init
F_Vdd
–
–
–
–
Output Load Sensitivity
F_load
–
–
–
Frequency Stability over
Temperature
F_stab
-0.5
-1.0
ΔF/ΔT
-2.5
–
–
–
Dynamic Frequency Change during
Temperature Ramp
F_dynamic
–
–
–
One-Year Aging
20-Year Aging
F_1y
F_20y
–
–
Typ.
–
–
–
–
±1
±7.10
±11.83
±28.40
±0.81
±1.35
±3.24
–
–
–
±15
±25
±60
±0.13
±0.21
±0.50
±1
±2
Max.
60
+70
+85
+105
–
–
–
–
–
–
–
+0.5
+1.0
+2.5
–
–
–
–
–
–
–
–
Unit
MHz
°C
°C
°C
ppm
ppb
ppb
ppb
ppb
ppb
ppb
ppm
ppm
ppm
ppb/°C
ppb/°C
ppb/°C
ppb/s
ppb/s
ppb/s
ppm
ppm
±0.5 ppm F_stab, 0.5°C/min ramp rate, -40 to 105 ºC
±1.0 ppm F_stab, 0.5°C/min ramp rate, -40 to 105 ºC
±2.5 ppm F_stab, 0.5°C/min ramp rate, -40 to 105 ºC
±0.5 ppm F_stab, 0.5°C/min ramp rate, -40 to 105 ºC
±1.0 ppm F_stab, 0.5°C/min ramp rate, -40 to 105 ºC
±2.5 ppm F_stab, 0.5°C/min ramp rate, -40 to 105 ºC
At 25°C, after 2-days of continued operation. Aging is
measured with respect to day 3.
At 25°C, after 2-days of continued operation. Aging is
measured with respect to day 3.
AEC-Q100 Grade4, ambient temperature
AEC-Q100 Grade3, ambient temperature
AEC-Q100 Grade2, ambient temperature
Initial frequency at 25°C inclusive of solder-down shift
at 48 hours after 2 reflows
±0.5 ppm F_stab, Vdd ±5%
±1.0ppm F_stab, Vdd ±5%
±2.5 ppm F_stab, Vdd ±5%
±0.5 ppm F_stab. LVCMOS output, 15 pF ±10%. Clipped
sinewave output, 10kΩ || 10 pF ±10%
±1.0 ppm F_stab. LVCMOS output, 15 pF ±10%. Clipped
sinewave output, 10kΩ || 10 pF ±10%
±2.5 ppm F_stab. LVCMOS output, 15 pF ±10%. Clipped
sinewave output, 10kΩ || 10 pF ±10%
Referenced to (max frequency + min frequency)/2 over the
rated temperature range. Vc=Vdd/2 for VCTCXO
Condition
Frequency Coverage
Temperature Range
Frequency Stability
Frequency vs. Temperature Slope
LVCMOS Output Characteristics
Duty Cycle
Rise/Fall Time
Output Voltage High
Output Voltage Low
Output Impedance
Output Voltage Swing
Rise/Fall Time
Start-up Time
DC
Tr, Tf
VOH
VOL
Z_out_c
V_out
Tr, Tf
T_start
45
–
90%
–
–
0.8
–
–
–
1.2
–
–
20
–
3.5
2.5
55
–
–
10%
–
1.2
–
3.5
%
ns
Vdd
Vdd
Ohms
V
ns
ms
10% - 90% Vdd
IOH = +3mA
IOL = -3mA
Impedance looking into output buffer
Clipped sinewave output, 10kΩ || 10 pF ±10%
20% - 80% Vdd, F = 19.2 MHz
Time to first pulse, measured from the time Vdd reaches
90% of its final value. Vdd ramp time = 100 µs from 0V to
Vdd
F_nom=10 MHz. See
Timing Diagrams
section below.
Time to first accurate pulse within rated stability, measured
from the time Vdd reaches 90% of its final value. Vdd
ramp time = 100 µs
Clipped Sinewave Output Characteristics
Start-up Characteristics
Output Enable Time
First Pulse Accuracy
T_oe
T_stability
–
–
–
5
680
–
ns
ms
Rev 0.3
Page 4 of 36
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SiT5186
AEC-Q100, 1 to 60 MHz, ±0.5 to ±2.5 ppm, Elite Platform™ Super-TCXO
Table 2. DC Characteristics
Parameters
Supply Voltage
Symbol
Vdd
Min.
2.25
2.52
2.7
2.97
Current Consumption
OE Disable Current
Idd
I_od
–
–
–
–
Typ.
2.5
2.8
3.0
3.3
44
48
43
47
Max.
2.75
3.08
3.3
3.63
53
57
51
55
Unit
V
V
V
V
mA
mA
mA
mA
F_nom = 19.2 MHz, No Load, TCXO and DCTCXO modes
F_nom = 19.2 MHz, No Load, VCTCXO mode
OE = GND, output weakly pulled down. TCXO, DCTCXO
OE = GND, output weakly pulled down. VCTCXO mode
Condition
Contact
SiTime
for 2.25V to 3.63V continuous supply
voltage support.
Supply Voltage
Current Consumption
Table 3. Input Characteristics
Parameters
Input Impedance
Input High Voltage
Input Low Voltage
Symbol
Z_in
VIH
VIL
Min.
75
70%
–
±6.25
±6.25
±10
±12.5
±25
±50
±80
±100
±125
±150
±200
±400
±600
±800
±1200
±1600
±3200
±2.75
±2.25
±0.75
Upper Control Voltage
Lower Control Voltage
Control Voltage Input Impedance
Control Voltage Input Bandwidth
Frequency Control Polarity
Pull Range Linearity
Bus Frequency
VC_U
VC_L
VC_z
VC_bw
F_pol
PR_lin
F_I2C
–
–
–
–
Input Voltage Low
Input Voltage High
Output Voltage Low
Input Leakage current
Input Capacitance
VIL_I2C
VIH_I2C
VOL_I2C
I
L
C
IN
–
70%
–
0.5
–
90%
–
8
–
Typ.
–
–
–
–
Max.
–
–
30%
–
Unit
kΩ
Vdd
Vdd
ppm
VCTCXO mode; contact
SiTime
for ±12.5 and ±25 ppm.
Internal pull up to Vdd
Condition
Input Characteristics
–
OE Pin
Frequency Tuning Range – Voltage Control or I
2
C mode
Pull Range
PR
–
–
ppm
DCTCXO mode
Absolute Pull Range
[3]
APR
–
–
–
–
–
–
10
Positive
0.5
100
400
1000
–
–
–
–
–
–
–
–
–
10%
–
–
1.0
–
–
–
30%
–
0.4
24
5
ppm
ppm
ppm
Vdd
Vdd
MΩ
kHz
%
kHz
kHz
kHz
Vdd
Vdd
V
µA
pF
±0.5 ppm F_stab, DCTCXO, VCTCXO for PR = ±6.25 ppm
±1.0 ppm F_stab, DCTCXO, VCTCXO for PR = ±6.25 ppm
±2.5 ppm F_stab, DCTCXO, VCTCXO for PR = ±6.25 ppm
VCTCXO mode
VCTCXO mode
VCTCXO mode
VCTCXO mode; contact
SiTime
for other bandwidth options
VCTCXO mode
VCTCXO mode
-40 to 105
°C
-40 to 105
°C
-40 to 85
°C
DCTCXO mode
DCTCXO mode
DCTCXO mode
0.1 V
DD
< VOUT < 0.9 V
DD.
Includes typical leakage current
from 200 kΩ pull resister to VDD. DCTCXO mode
DCTCXO mode
I
2
C Interface Characteristics, 200 Ohm, 550 pF (Max I
2
C Bus Load)
Note:
3. APR = PR – initial tolerance – 20-year aging – frequency stability over temperature. Refer to
Table 17
for APR with respect to other pull range options.
Rev 0.3
Page 5 of 36
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