Freescale Semiconductor
Technical Data
Document Number: MPC8313EEC
Rev. 2.1, 12/2008
MPC8313E
™
PowerQUICC II Pro Processor
Hardware Specifications
This document provides an overview of the MPC8313E
PowerQUICC™ II Pro processor features, including a block
diagram showing the major functional components. The
MPC8313E is a cost-effective, low-power, highly integrated
host processor that addresses the requirements of several
printing and imaging, consumer, and industrial applications,
including main CPUs and I/O processors in printing systems,
networking switches and line cards, wireless LANs
(WLANs), network access servers (NAS), VPN routers,
intelligent NIC, and industrial controllers. The MPC8313E
extends the PowerQUICC™ family, adding higher CPU
performance, additional functionality, and faster interfaces
while addressing the requirements related to time-to-market,
price, power consumption, and package size.
NOTE
The information in this document is accurate for
revisions 1.0, 2.x, and later. See
Section 24.1, “Part
Numbers Fully Addressed by this Document.”
Contents
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 6
Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 10
Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 12
RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 13
DDR and DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . 14
DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Ethernet: Three-Speed Ethernet, MII Management . 21
High-Speed Serial Interfaces (HSSI) . . . . . . . . . . . . 36
USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Enhanced Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . 47
JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
I
2
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
IPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . 63
Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
System Design Information . . . . . . . . . . . . . . . . . . . 88
Document Revision History . . . . . . . . . . . . . . . . . . . 94
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 97
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
© Freescale Semiconductor, Inc., 2007, 2008. All rights reserved.
Overview
1
Overview
The MPC8313E incorporates the e300c3 core, which includes 16 Kbytes of L1 instruction and data caches
and on-chip memory management units (MMUs). The MPC8313E has interfaces to dual enhanced
three-speed 10/100/1000 Mbps Ethernet controllers, a DDR1/DDR2 SDRAM memory controller, an
enhanced local bus controller, a 32-bit PCI controller, a dedicated security engine, a USB 2.0 dual-role
controller and an on-chip full-speed PHY, a programmable interrupt controller, dual I
2
C controllers, a
4-channel DMA controller, and a general-purpose I/O port. A block diagram of the MPC8313E is shown
in
Figure 1.
DUART
Dual I
2
C
Timers
GPIO
e300c3 Core w/FPU and
Power Management
Interrupt
Controller
16-KB
I-Cache
16-KB
D-Cache
Local Bus,
SPI
DDR1/DDR2
Controller
I/O Sequencer
(IOS)
PCI
DMA
Security Engine 2.2
USB 2.0
Host/Device/OTG
ULPI
On-Chip
FS PHY
Gb Ethernet
MAC
Gb Ethernet
MAC
Note:
The MPC8313 does not include a security engine.
Figure 1. MPC8313E Block Diagram
The MPC8313E security engine (SEC 2.2) allows CPU-intensive cryptographic operations to be offloaded
from the main CPU core. The security-processing accelerator provides hardware acceleration for the DES,
3DES, AES, SHA-1, and MD-5 algorithms.
1.1
MPC8313E Features
The following features are supported in the MPC8313E:
• Embedded PowerPC™ e300 processor core built on Power Architecture™ technology; operates at
up to 333 MHz.
• High-performance, low-power, and cost-effective host processor
• DDR1/DDR2 memory controller—one 16-/32-bit interface at up to 333 MHz supporting both
DDR1 and DDR2
• 16-Kbyte instruction cache and 16-Kbyte data cache, a floating point unit, and two integer units
• Peripheral interfaces such as 32-bit PCI interface with up to 66-MHz operation, 16-bit enhanced
local bus interface with up to 66-MHz operation, and USB 2.0 (full speed) with an on-chip PHY.
• Security engine provides acceleration for control and data plane security protocols
• Power management controller for low-power consumption
• High degree of software compatibility with previous-generation PowerQUICC processor-based
designs for backward compatibility and easier software migration
MPC8313E PowerQUICC
™
II Pro Processor Hardware Specifications, Rev. 2.1
2
Freescale Semiconductor
Overview
1.2
Serial Interfaces
The following interfaces are supported in the MPC8313E: dual UART, dual I
2
C, and an SPI interface
1.3
Security Engine
The security engine is optimized to handle all the algorithms associated with IPSec, IEEE Std 802.11i®,
and iSCSI. The security engine contains one crypto-channel, a controller, and a set of crypto execution
units (EUs). The execution units are as follows:
• Data encryption standard execution unit (DEU), supporting DES and 3DES
• Advanced encryption standard unit (AESU), supporting AES
• Message digest execution unit (MDEU), supporting MD5, SHA1, SHA-224, SHA-256, and
HMAC with any algorithm
• One crypto-channel supporting multi-command descriptor chains
1.4
DDR Memory Controller
The MPC8313E DDR1/DDR2 memory controller includes the following features:
• Single 16- or 32-bit interface supporting both DDR1 and DDR2 SDRAM
• Support for up to 333 MHz
• Support for two physical banks (chip selects), each bank independently addressable
• 64-Mbit to 1-Gbit devices with x8/x16/x32 data ports (no direct x4 support)
• Support for one 16-bit device or two 8-bit devices on a 16-bit bus, or one 32-bit device or two
16-bit devices on a 32-bit bus
• Support for up to 16 simultaneous open pages
• Supports auto refresh
• On-the-fly power management using CKE
• 1.8-/2.5-V SSTL2 compatible I/O
1.5
PCI Controller
The MPC8313E PCI controller includes the following features:
• PCI specification revision 2.3 compatible
• Single 32-bit data PCI interface operates at up to 66 MHz
• PCI 3.3-V compatible (not 5-V compatible)
• Support for host and agent modes
• On-chip arbitration, supporting three external masters on PCI
• Selectable hardware-enforced coherency
MPC8313E PowerQUICC
™
II Pro Processor Hardware Specifications, Rev. 2.1
Freescale Semiconductor
3
Overview
1.6
USB Dual-Role Controller
The MPC8313E USB controller includes the following features:
• Supports USB on-the-go mode, which includes both device and host functionality, when using an
external ULPI (UTMI + low-pin interface) PHY
• Compatible with
Universal Serial Bus Specification, Rev. 2.0
• Supports operation as a stand-alone USB device
— Supports one upstream facing port
— Supports three programmable USB endpoints
• Supports operation as a stand-alone USB host controller
— Supports USB root hub with one downstream-facing port
— Enhanced host controller interface (EHCI) compatible
• Supports full-speed (12 Mbps), and low-speed (1.5 Mbps) operation. Low-speed operation is
supported only in host mode.
• Supports UTMI + low pin interface (ULPI) or on-chip USB 2.0 full-speed PHY
1.7
Dual Enhanced Three-Speed Ethernet Controllers (eTSECs)
The MPC8313E eTSECs include the following features:
• Two RGMII/SGMII/MII/RMII/RTBI interfaces
• Two controllers designed to comply with IEEE Std 802.3®, 802.3u®, 802.3x®, 802.3z®,
802.3au®, and 802.3ab®
• Support for Wake-on-Magic Packet™, a method to bring the device from standby to full operating
mode
• MII management interface for external PHY control and status
• Three-speed support (10/100/1000 Mbps)
• On-chip high-speed serial interface to external SGMII PHY interface
• Support for IEEE Std 1588™
• Support for two full-duplex FIFO interface modes
• Multiple PHY interface configuration
• TCP/IP acceleration and QoS features available
• IP v4 and IP v6 header recognition on receive
• IP v4 header checksum verification and generation
• TCP and UDP checksum verification and generation
• Per-packet configurable acceleration
• Recognition of VLAN, stacked (queue in queue) VLAN, IEEE Std 802.2®, PPPoE session, MPLS
stacks, and ESP/AH IP-security headers
• Transmission from up to eight physical queues.
• Reception to up to eight physical queues
MPC8313E PowerQUICC
™
II Pro Processor Hardware Specifications, Rev. 2.1
4
Freescale Semiconductor
Overview
•
•
•
•
•
•
Full- and half-duplex Ethernet support (1000 Mbps supports only full-duplex):
— IEEE 802.3 full-duplex flow control (automatic PAUSE frame generation or
software-programmed PAUSE frame generation and recognition)
— Programmable maximum frame length supports jumbo frames (up to 9.6 Kbytes) and
IEEE 802.1 virtual local area network (VLAN) tags and priority
— VLAN insertion and deletion
– Per-frame VLAN control word or default VLAN for each eTSEC
– Extracted VLAN control word passed to software separately
— Retransmission following a collision
— CRC generation and verification of inbound/outbound packets
— Programmable Ethernet preamble insertion and extraction of up to 7 bytes
MAC address recognition:
— Exact match on primary and virtual 48-bit unicast addresses
– VRRP and HSRP support for seamless router fail-over
— Up to 16 exact-match MAC addresses supported
— Broadcast address (accept/reject)
— Hash table match on up to 512 multicast addresses
— Promiscuous mode
Buffer descriptors backward compatible with MPC8260 and MPC860T 10/100 Ethernet
programming models
RMON statistics support
10-Kbyte internal transmit and 2-Kbyte receive FIFOs
MII management interface for control and status
1.8
Programmable Interrupt Controller (PIC)
The programmable interrupt controller (PIC) implements the necessary functions to provide a flexible
solution for general-purpose interrupt control. The PIC programming model supports 5 external and 34
internal discrete interrupt sources. Interrupts can also be redirected to an external interrupt controller.
1.9
Power Management Controller (PMC)
The MPC8313E power management controller includes the following features:
• Provides power management when the device is used in both host and agent modes
• Supports PCI power management 1.2 D0, D1, D2, D3hot, and D3cold states
• On-chip split power supply controlled through external power switch for minimum standby power
• Support for PME generation in PCI agent mode, PME detection in PCI host mode
• Supports wake-up from Ethernet (Magic Packet), USB, GPIO, and PCI (PME input as host)
MPC8313E PowerQUICC
™
II Pro Processor Hardware Specifications, Rev. 2.1
Freescale Semiconductor
5
Analog electronics
京公网安备 11010802033920号
EEWORLD
