ispClock 5600A Family
™
In-System Programmable, Enhanced Zero-Delay
Clock Generator with Universal Fan-Out Buffer
June 2008
Data Sheet DS1019
Features
■
■
■
■
8MHz to 400MHz Input/Output Operation
Low Output to Output Skew (<50ps)
Low Jitter Peak-to-Peak
Up to 20 Programmable Fan-out Buffers
• Programmable output standards and individual
enable controls
- LVTTL, LVCMOS, HSTL, eHSTL, SSTL,
LVDS, LVPECL, Differential HSTL, SSTL
• Programmable output impedance
- 40 to 70
Ω
in 5
Ω
increments
• Programmable slew rate
• Up to 10 banks with individual V
CCO
and GND
- 1.5V, 1.8V, 2.5V, 3.3V
■
Up to Five Clock Frequency Domains
■
Flexible Clock Reference and External
Feedback Inputs
• Programmable input standards
- LVTTL, LVCMOS, SSTL, HSTL, LVDS,
LVPECL, Differential HSTL, SSTL
• Clock A/B selection multiplexer
• Feedback A/B selection multiplexer
• Programmable termination
■
All Inputs and Outputs are Hot Socket
Compliant
■
Four User-programmable Profiles Stored in
E
2
CMOS
®
Memory
• Supports both test and multiple operating
configurations
■
Fully Integrated High-Performance PLL
• Programmable lock detect
• Multiply and divide ratio controlled by
- Input divider (1 to 40)
- Feedback divider (1 to 40)
- Five output dividers (2 to 80)
• Programmable on-chip loop filter
• Compatible with spread spectrum clocks
■
Full JTAG Boundary Scan Test In-System
Programming Support
■
Exceptional Power Supply Noise Immunity
■
Commercial (0 to 70°C) and Industrial
(-40 to 85°C) Temperature Ranges
■
100-pin and 48-pin TQFP Packages
■
Applications
• Circuit board common clock generation and
distribution
• PLL-based frequency generation
• High fan-out clock buffer
• Zero-delay clock buffer
■
Precision Programmable Phase Adjustment
(Skew) Per Output
• 16 settings; minimum step size 156ps
- Locked to VCO frequency
• Up to +/- 12ns skew range
• Coarse and fine adjustment modes
Product Family Block Diagram
LOCK DETECT
OUTPUT
DIVIDERS
BYPASS
MUX
*
V0
V1
V2
V3
V4
PLL CORE
Internal/External
Feedback
Select
*
OUTPUT
ROUTING
MATRIX
SKEW
CONTROL
OUTPUT
DRIVERS
REFERENCE
INPUTS
M
PHASE/
FREQUENCY
DETECTOR
FILTER
VCO
N
FEEDBACK
INPUTS
JTAG
INTERFACE
&
E
2
CMOS
MEMORY
Multiple Profile
Management Logic
0
1
2
3
INTERNAL FEEDBACK PATH
* Input Available only on ispClock5620A
© 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
1-1
DS1019_01.4
CLOCK OUTPUTS
Lattice Semiconductor
ispClock5600A Family Data Sheet
General Description and Overview
The ispClock5610A and ispClock5620A are in-system-programmable high-fanout enhanced zero delay clock gen-
erators designed for use in high performance communications and computing applications. The ispClock5610A
provides up to 10 single-ended or five differential clock outputs, while the ispClock5620A provides up to 20 single-
ended or 10 differential clock outputs. Each pair of outputs may be independently configured to support separate
I/O standards (LVDS, LVPECL, LVTTL, LVCMOS, SSTL, HSTL) and output frequency. In addition, each output
provides independent programmable control of termination, slew-rate, and timing skew. All configuration informa-
tion is stored on-chip in non-volatile E
2
CMOS memory.
The ispClock5600A’s PLL and divider systems supports the synthesis of multiple clock frequencies derived from
the reference input through the provision of programmable input and feedback dividers. A set of five post-PLL V-
dividers provides additional flexibility by supporting the generation of five separate output frequencies. Loop feed-
back may be taken internally from the output of any of the five V-dividers, or externally through FBKA+/- or FBKB+/-
pins.
The core functions of all members of the ispClock5600A family are identical, the differences between devices being
restricted to the number of inputs and outputs, as shown in the following table. Figures 1 and 2 show functional
block diagrams of the ispClock5610A and ispClock5620A.
Table 1-1. ispClock5600A Family Members
Device
ispClock5610A
ispClock5620A
Ref. Input Pairs
1
2
Feedback Input Pairs
1
2
Clock Outputs
10
20
Figure 1-1. ispClock5610A Functional Block Diagram
PS0
PS1
LOCK
RESET
PLL_BYPASS
SGATE
GOE
OEX
OEY
Profile Select
Control
OUTPUT ENABLE CONTROLS
0
1
2
3
LOCK
DETECT
OUTPUT
DIVIDERS
V0
(2-80)
OUTPUT ROUTING
MATRIX
SKEW
CONTROL
OUTPUT
DRIVERS
BANK_0
BANK_0
BANK_1
BANK_1
BANK_2
BANK_2
BANK_3
BANK_3
BANK_4
BANK_4
INPUT
DIVIDER
REFA+
REFA-
REFVTT
M
(1-40)
1
V1
(2-80)
PHASE
DETECT
LOOP
FILTER
V2
(2-80)
VCO
0
V3
(2-80)
N
(1-40)
FEEDBACK
DIVIDER
V4
(2-80)
E
2
Configuration
FBKA+
FBKA -
FBKVTT
JTAG INTERFACE
FEEDBACK
SKEW ADJUST
TDI
TMS
TCK
TDO
1-2
Lattice Semiconductor
Figure 1-2. ispClock5620A Functional Block Diagram
PS0
PS1
LOCK
RESET
PLL_BYPASS
SGATE
GOE
ispClock5600A Family Data Sheet
OEX
OEY
SKEW
CONTROL
OUTPUT
DRIVERS
BANK_0A
BANK_0B
BANK_1A
Profile Select
Control
OUTPUT ROUTING
MATRIX
OUTPUT ENABLE CONTROLS
0
1
2
3
LOCK
DETECT
BANK_1B
BANK_2A
BANK_2B
OUTPUT
DIVIDERS
V0
BANK_3A
BANK_3B
BANK_4A
REFSEL
REFA+
REFA-
0
(2-80)
INPUT
DIVIDER
M
(1-40)
1
V1
(2-80)
BANK_4B
REFVTT
1
REFB+
REFB-
PHASE
DETECT
LOOP
FILTER
V2
(2-80)
VCO
0
V3
(2-80)
SKEW
CONTROL
OUTPUT
DRIVERS
BANK_5A
BANK_5B
N
(1-40)
FEEDBACK
DIVIDER
V4
(2-80)
FBKSEL
FBKA+
FBKA-
0
BANK_6A
BANK_6B
E
2
Configuration
BANK_7A
BANK_7B
BANK_8A
BANK_8B
BANK_9A
JTAG INTERFACE
FEEDBACK
SKEW ADJUST
BANK_9B
FBKVTT
1
FBKB+
FBKB-
TDI
TMS
TCK
TDO
1-3
Lattice Semiconductor
ispClock5600A Family Data Sheet
Absolute Maximum Ratings
ispClock5600A
Core Supply Voltage V
CCD
. . . . . . . . . . . . . . . . . . . -0.5 to 5.5V
PLL Supply Voltage V
CCA
. . . . . . . . . . . . . . . . . . . . -0.5 to 5.5V
JTAG Supply Voltage V
CCJ
. . . . . . . . . . . . . . . . . . . -0.5 to 5.5V
Output Driver Supply Voltage V
CCO
. . . . . . . . . . . . -0.5 to 4.5V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 4.5V
Output Voltage
1
. . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 4.5V
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . -65 to 150°C
Junction Temperature with power supplied . . . . . . -40 to 130°C
1. When applied to an output when in high-Z condition
Recommended Operating Conditions
ispClock5600A
Symbol
V
CCD
V
CCJ
V
CCA
V
CCXSLEW
T
JOP
T
A
Parameter
Core Supply Voltage
JTAG I/O Supply Voltage
Analog Supply Voltage
V
CC
Turn-on Ramp Rate
Operating Junction Temperature
Ambient Operating Temperature
All supply pins
Commercial
Industrial
Commercial
Industrial
Conditions
Min.
3.0
2.25
3.0
—
0
-40
0
-40
Max.
3.6
3.6
3.6
0.33
130
130
70
1
85
1
Units
V
V
V
V/µs
°C
°C
1. Device power dissipation may also limit maximum ambient operating temperature.
Recommended Operating Conditions – V
CCO
vs. Logic Standard
V
CCO
(V)
Logic Standard
LVTTL
LVCMOS 1.8V
LVCMOS 2.5V
LVCMOS 3.3V
SSTL1.8
SSTL2 Class 1
SSTL3 Class 1
HSTL Class 1
eHSTL Class 1
LVPECL (Differential)
LVDS
V
CCO
= 2.5V
V
CCO
= 3.3V
Min.
3.0
1.71
2.375
3.0
1.71
2.375
3.0
1.425
1.71
3.0V
2.375
3.0
Typ.
3.3
1.8
2.5
3.3
1.8
2.5
3.3
1.5
1.8
3.3V
2.5V
3.3
Max.
3.6
1.89
2.625
3.6
1.89
2.625
3.6
1.575
1.89
3.6V
2.625
3.6
Min.
—
—
—
—
0.84
1.15
1.30
0.68
0.84
—
—
—
V
REF
(V)
Typ.
—
—
—
—
0.90
1.25
1.50
0.75
0.90
—
—
—
Max.
—
—
—
—
0.95
1.35
1.70
0.90
0.95
—
—
—
Min.
—
—
—
—
—
V
REF
- 0.04
V
REF
- 0.05
—
—
—
—
—
V
TT
(V)
Typ.
—
—
—
—
0.5 x V
CCO
V
REF
V
REF
0.5 x V
CCO
0.5 x V
CCO
—
—
—
Max.
—
—
—
—
—
V
REF
+ 0.04
V
REF
+ 0.05
—
—
—
—
—
Note: ‘—’ denotes V
REF
or V
TT
not applicable to this logic standard
1-4
Lattice Semiconductor
ispClock5600A Family Data Sheet
E
2
CMOS Memory Write/Erase Characteristics
Parameter
Erase/Reprogram Cycles
Conditions
Min.
1000
Typ.
—
Max.
—
Units
Performance Characteristics – Power Supply
Symbol
I
CCD
I
CCA
Parameter
Core Supply Current
3
Analog Supply Current
3
Output Driver Supply Current
(per Bank)
Conditions
ispClock5610A f
VCO
= 800MHz
ispClock5620A f
VCO
= 800MHz
f
VCO
= 800MHz
V
CCO
= 1.8V
1
, LVCMOS, f
OUT
= 266MHz
I
CCO
V
CCO
= 2.5V
1
, LVCMOS, f
OUT
= 266MHz
V
CCO
= 3.3V , LVCMOS, f
OUT
= 266MHz
V
CCO
= 3.3V , LVDS, f
OUT
= 400MHz
V
CCJ
= 1.8V
I
CCJ
JTAG I/O Supply Current (static) V
CCJ
= 2.5V
V
CCJ
= 3.3V
1. Supply current consumed by each bank, both outputs active, 5pF load.
2. Supply current consumed by each bank, 100
Ω
, 5pf differential load.
3. All unused REFCLK and feedbacks connected to ground.
2
1
Typ.
110
130
5.5
16
21
27
8
Max.
125
150
7
18
27
38
10
300
400
400
Units
mA
mA
mA
mA
mA
mA
mA
µA
µA
µA
DC Electrical Characteristics – Single-ended Logic
V
IL
(V)
Logic Standard
LVTTL/LVCMOS 3.3V
LVCMOS 1.8V
LVCMOS 2.5V
SSTL2 Class 1
SSTL3 Class 1
HSTL Class 1
eHSTL Class 1
Min.
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
Max.
0.8
0.68
0.7
V
REF
- 0.2
V
REF
- 0.1
V
REF
- 0.1
2
1.07
1.7
V
REF
+ 0.2
V
REF
+ 0.1
V
REF
+ 0.1
V
IH
(V)
Min.
Max.
3.6
3.6
3.6
3.6
3.6
3.6
3.6
V
OL
Max. (V) V
OH
Min. (V)
0.4
0.4
0.4
0.54
2
0.9
0.4
0.4
2
3
3
I
OL
(mA)
12
2, 3
12
2, 3
12
2, 3
7.6
8
8
8
I
OH
(mA)
-12
2, 3
-12
2, 3
-12
2, 3
-7.6
-8
-8
-8
V
CCO
- 0.4
V
CCO
- 0.4
V
CCO
- 0.4
V
CCO
- 0.81
1
V
CCO
- 1.3
V
CCO
- 0.4
V
CCO
- 0.4
1
2
2
V
REF
- 0.18 V
REF
+ 0.18
1. Specified for 40Ω internal series output termination.
2. Specified for
≈20Ω
internal series output termination, fast slew rate setting.
3. For slower slew rate setting I
OH
, I
OL
= 8mA.
1-5
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