EEWORLDEEWORLDEEWORLD

Part Number

Search
 PDF

C1210R564J3RACT100

Description
Ceramic Capacitor, Ceramic,
CategoryPassive components    capacitor   
File Size2MB,21 Pages
ManufacturerKEMET
Websitehttp://www.kemet.com
Download Datasheet Parametric View All

C1210R564J3RACT100 Overview

Ceramic Capacitor, Ceramic,

C1210R564J3RACT100 Parametric

Parameter NameAttribute value
MakerKEMET
package instruction, 1210
Reach Compliance Codecompli
ECCN codeEAR99
capacitance0.56 µF
Capacitor typeCERAMIC CAPACITOR
dielectric materialsCERAMIC
high1.55 mm
JESD-609 codee3
length3.3 mm
Installation featuresSURFACE MOUNT
multi-layerYes
negative tolerance5%
Number of terminals2
Maximum operating temperature175 °C
Minimum operating temperature-55 °C
Package formSMT
method of packingTR, Embossed Plastic, 7 Inch
positive tolerance5%
Rated (DC) voltage (URdc)25 V
size code1210
surface mountYES
Temperature characteristic codeX7R
Temperature Coefficient15% ppm/°C
Terminal surfaceMatte Tin (Sn) - with Nickel (Ni) barrie
Terminal shapeWRAPAROUND
width2.6 mm
National Undergraduate Electronic Design Competition Commonly Used Modules and Related Devices Data Album
[i=s]This post was last edited by Rambo on 2019-7-16 09:49[/i]A collection of commonly used modules and related device data for the National Undergraduate Electronic Design Competition. 114 high-quali...
兰博 Electronics Design Contest
Designing 3G mobile phones requires choosing the best IC integration method
SiPs and SoCs are currently in vogue. Understand whether they''re right for your design.(www.52rd.com)By Bill Krenik, Dennis Buss, and Peter Rickert, Texas Instruments The era of the voice-only mobile...
fly RF/Wirelessly
TOP223 chip
Looking for drawing software suitable for TOP223 chip...
生气的青柠 Analog electronics
The concept and basic principle of PWM "dead zone"
[size=4] Dead zone means that after the upper half bridge is turned off, the lower half bridge is turned on after a delay of a period of time, or after the lower half bridge is turned off, the upper h...
qwqwqw2088 Analogue and Mixed Signal
Effects of Improper Use of Derived Clocks on Logic Timing
After the project code is compiled, the following information is printed: Info: Clock "CLK48M" has Internalfmax of 67.47 MHz between source register "GLUE_LGC:glue|MCLK" and destination register "img_...
Jacktang DSP and ARM Processors
Consulting on segment LCD issues
That is, the address of SEG0 and SEG1 is 00H. If I want to light up all segments of 5, but the upper four bits of 5 are at address 04H, and the lower four bits are at address 05H. It is inconvenient t...
一百年后的自己 51mcu

Technical ResourceMore

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2024 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号