1. Call Factory for other package options available.
2. For optional
512 Byte Page size with 256 KB
Block size, see the Ordering Information.
3. For optional dedicated WP# with dedicated RESET#,
see the Ordering table.
Integrated Silicon Solution, Inc.- www.issi.com
Rev.00D
02/25/2020
2
IS25LP512MG
IS25WP512MG
GENERAL DESCRIPTION
The IS25LP512MG and IS25WP512MG Serial Flash memory offers a versatile storage solution with high flexibility
and performance in a simplified pin count package. ISSI’s “Industry Standard Serial Interface” Flash is for systems
that require limited space, a low pin count, and low power consumption. The device is accessed through a 4-wire
SPI Interface consisting of a Serial Data Input (SI), Serial Data Output (SO), Serial Clock (SCK), and Chip Enable
(CE#) pins, which can also be configured to serve as multi-I/O (see pin descriptions).
The device supports Dual and Quad I/O as well as standard, Dual Output, and Quad Output SPI. Clock frequencies
of up to 166MHz allow for equivalent clock rates of up to 664MHz (166MHz x 4) which equates to 83Mbytes/s of
data throughput. The IS25xP series of Flash adds support for DTR (Double Transfer Rate) commands that transfer
addresses and read data on both edges of the clock. These transfer rates can outperform 16-bit Parallel Flash
memories allowing for efficient memory access to support XIP (execute in place) operation.
Initial state of the memory array is erased (all bits are set to 1) when shipped from the factory.
QPI (Quad Peripheral Interface) supports 2-cycle instruction further reducing instruction times. Pages can be
erased in groups of 4Kbyte sectors, 32Kbyte blocks, 64K/256Kbyte blocks, and/or the entire chip. The uniform
sector and block architecture allows for a high degree of flexibility so that the device can be utilized for a broad
variety of applications requiring solid data retention.
GLOSSARY
Standard SPI
In this operation, a 4-wire SPI Interface is utilized, consisting of Serial Data Input (SI), Serial Data Output (SO),
Serial Clock (SCK), and Chip Enable (CE#) pins. Instructions are sent via the SI pin to encode instructions,
addresses, or input data to the device on the rising edge of SCK. The SO pin is used to read data or to check the
status of the device. This device supports SPI bus operation modes (0,0) and (1,1).
Mutil I/O SPI
Multi-I/O operation utilizes an enhanced SPI protocol to allow the device to function with Dual Output, Dual Input
and Output, Quad Output, and Quad Input and Output capability. Executing these instructions through SPI mode
will achieve double or quadruple the transfer bandwidth for READ and PROGRAM operations.
QPI
The device enables QPI protocol by issuing an “Enter QPI mode (35h)” command. The QPI mode uses four IO
pins for input and output to decrease SPI instruction overhead and increase output bandwidth. SI and SO pins
become bidirectional IO0 and IO1, and WP# and HOLD# pins become IO2 and IO3 respectively during QPI mode.
Issuing an “Exit QPI (F5h) command will cause the device to exit QPI mode. Power Reset or Hardware/Software
Reset can also return the device into the standard SPI mode.
DTR
In addition to SPI and QPI features, the device also supports Fast READ DTR operation. Fast READ DTR operation
allows high data throughput while running at lower clock frequencies. Fast READ DTR operation uses both rising
and falling edges of the clock for address inputs, and data outputs, resulting in reducing input and output cycles
by half.
Integrated Silicon Solution, Inc.- www.issi.com
Rev.00D
02/25/2020
3
IS25LP512MG
IS25WP512MG
TABLE OF CONTENTS
FEATURES ........................................................................................................................................................... 2
GENERAL DESCRIPTION ................................................................................................................................... 3
TABLE OF CONTENTS ........................................................................................................................................ 4
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