MT51256L-70 datasheet, PDF - EEWORLD Datasheet

MT51256L-70: DescriptionIC,SRAM,32KX8,CMOS,LDCC,32PIN,CERAMIC; Categorystorage storage; File Size318KB，9 Pages; ManufacturerIntel; Websitehttp://www.intel.com/

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MT51256L-70 Overview

IC,SRAM,32KX8,CMOS,LDCC,32PIN,CERAMIC

Parameter Name	Attribute value
Maker	Intel
package instruction	QCCJ, LDCC32,.45X.7
Reach Compliance Code	unknow
Maximum access time	70 ns
I/O type	COMMON
JESD-30 code	R-XQCC-J32
JESD-609 code	e0
memory density	262144 bi
Memory IC Type	STANDARD SRAM
memory width	8
Number of terminals	32
word count	32768 words
character code	32000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
organize	32KX8
Output characteristics	3-STATE
Package body material	CERAMIC
encapsulated code	QCCJ
Encapsulate equivalent code	LDCC32,.45X.7
Package shape	RECTANGULAR
Package form	CHIP CARRIER
Parallel/Serial	PARALLEL
power supply	5 V
Certification status	Not Qualified
Filter level	38535Q/M;38534H;883B
Maximum standby current	0.0008 A
Minimum standby current	2 V
Maximum slew rate	0.125 mA
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD

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