v4.3
eX Family FPGAs
FuseLock
Leading Edge Performance
•
•
•
240 MHz System Performance
350 MHz Internal Performance
3.9 ns Clock-to-Out (Pad-to-Pad)
•
•
•
•
•
•
Specifications
•
•
•
•
3,000 to 12,000 Available System Gates
Maximum 512 Flip-Flops (Using CC Macros)
0.22µm CMOS Process Technology
Up to 132 User-Programmable I/O Pins
•
•
•
•
•
Features
•
•
•
•
•
•
High-Performance, Low-Power Antifuse FPGA
LP/Sleep Mode for Additional Power Savings
Advanced Small-Footprint Packages
Hot-Swap Compliant I/Os
Single-Chip Solution
Nonvolatile
Live on Power-Up
No Power-Up/Down Sequence Required for Supply
Voltages
Configurable Weak-Resistor Pull-Up or Pull-Down
for Tristated Outputs during Power-Up
Individual Output Slew Rate Control
2.5 V, 3.3 V, and 5.0 V Mixed-Voltage Operation
with 5.0V Input Tolerance and 5.0V Drive Strength
Software Design Support with Actel Designer and
Libero™ Integrated Design Environment (IDE)
Tools
Up to 100% Resource Utilization with 100% Pin
Locking
Deterministic Timing
Unique In-System Diagnostic and Verification
Capability with Silicon Explorer II
Boundary Scan Testing in Compliance with IEEE
Standard 1149.1 (JTAG)
Fuselock™ Secure Programming Technology
Prevents Reverse Engineering and Design Theft
Product Profile
Device
Capacity
System Gates
Typical Gates
Register Cells
Dedicated Flip-Flops
Maximum Flip-Flops
Combinatorial Cells
Maximum User I/Os
Global Clocks
Hardwired
Routed
Speed Grades
Temperature Grades*
Package
(by pin count)
TQFP
CSP
eX64
3,000
2,000
64
128
128
84
1
2
–F, Std, –P
C, I, A
64, 100
49, 128
eX128
6,000
4,000
128
256
256
100
1
2
–F, Std, –P
C, I, A
64, 100
49, 128
eX256
12,000
8,000
256
512
512
132
1
2
–F, Std, –P
C, I, A
100
128, 180
Note:
*Refer to the
eX Automotive Family FPGAs
datasheet for details on automotive temperature offerings.
June 2006
© 2006 Actel Corporation
i
eX Family FPGAs
Ordering Information
eX128
P
TQ
G
100
Application (Ambient Temperature Range)
Blank =
I=
A=
PP =
Commercial (0˚C to 70˚C)
Industrial (-40˚C to 85˚C)
Automotive (-40˚C to 125˚C)
Pre-production
Package Lead Count
Lead-Free Packaging
Blank = Standard Packaging
G = RoHS Compliant Packaging
Package Type
TQ = Thin Quad Flat Pack (0.5 mm pitch)
CS = Chip-Scale Package (0.8 mm pitch)
Speed Grade
Blank= Standard Speed
P = Approximately 30% Faster than Standard
F = Approximately 40% Slower than Standard
Part Number
eX64 = 64 Dedicated Flip-Flops (3,000 System Gates)
eX128 = 128 Dedicated Flip-Flops (6,000 System Gates)
eX256 = 256 Dedicated Flip-Flops (12,000 System Gates)
Plastic Device Resources
Device
eX64
eX128
eX256
TQFP 64-Pin
41
46
—
User I/Os (Including Clock Buffers)
TQFP 100-Pin
CSP 49-Pin
CSP 128-Pin
56
36
84
70
36
100
81
—
100
CSP 180-Pin
—
—
132
Note: Package Definitions:TQFP
= Thin Quad Flat Pack, CSP = Chip Scale Package
Temperature Grade Offerings
Device\Package
eX64
eX128
eX256
Notes:
C = Commercial
I = Industrial
A = Automotive
TQFP 64-Pin
C, I, A
C, I, A
C, I, A
TQFP 100-Pin
C, I, A
C, I, A
C, I, A
CSP 49-Pin
C, I, A
C, I, A
C, I, A
CSP 128-Pin
C, I, A
C, I, A
C, I, A
CSP 180-Pin
C, I, A
C, I, A
C, I, A
Speed Grade and Temperature Grade Matrix
C
I
A
Notes:
P = Approximately 30% faster than Standard
–F = Approximately 40% slower than Standard
Refer to the
eX Automotive Family FPGAs
datasheet for details on automotive temperature offerings.
–F
✓
Std
✓
✓
✓
–P
✓
✓
Contact your local Actel representative for device availability.
ii
v4.3
eX Family FPGAs
Table of Contents
eX Family FPGAs
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
eX Family Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Other Architectural Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
2.5V/3.3V/5.0V Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13
2.5V LVCMOS2 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14
3.3V LVTTL Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15
5.0V TTL Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17
Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17
eX Timing Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18
Output Buffer Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19
AC Test Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19
Input Buffer Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20
C-Cell Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20
Cell Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20
Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21
Temperature and Voltage Derating Factors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21
eX Family Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-26
Package Pin Assignments
64-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
100-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
49-Pin CSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
128-Pin CSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
180-Pin CSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
Datasheet Information
List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
Export Administration Regulations (EAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
v4.3
iii
eX Family FPGAs
eX Family FPGAs
General Description
The eX family of FPGAs is a low-cost solution for low-
power, high-performance designs. The inherent low
power attributes of the antifuse technology, coupled
with an additional low static power mode, make these
devices ideal for power-sensitive applications. Fabricated
with an advanced 0.22µm CMOS antifuse technology,
these devices achieve high performance with no power
penalty
.
impedance connection. Actel’s eX family provides two
types of logic modules, the register cell (R-cell) and the
combinatorial cell (C-cell).
The R-cell contains a flip-flop featuring asynchronous
clear, asynchronous preset, and clock enable (using the
S0 and S1 lines) control signals (Figure
1-1).
The R-cell
registers feature programmable clock polarity selectable
on a register-by-register basis. This provides additional
flexibility while allowing mapping of synthesized
functions into the eX FPGA. The clock source for the R-
cell can be chosen from either the hard-wired clock or
the routed clock.
The C-cell implements a range of combinatorial functions
up to five inputs (Figure
1-2 on page 1-2).
Inclusion of
the DB input and its associated inverter function enables
the implementation of more than 4,000 combinatorial
functions in the eX architecture in a single module.
Two C-cells can be combined together to create a flip-
flop to imitate an R-cell via the use of the CC macro. This
is particularly useful when implementing non-timing-
critical paths and when the design engineer is running
out of R-cells. More information about the CC macro can
be found in Actel’s
Maximizing Logic Utilization in eX, SX
and SX-A FPGA Devices Using CC Macros
application
note.
eX Family Architecture
Actel's eX family is implemented on a high-voltage twin-
well CMOS process using 0.22µm design rules. The eX
family architecture uses a “sea-of-modules” structure
where the entire floor of the device is covered with a
grid of logic modules with virtually no chip area lost to
interconnect elements or routing. Interconnection
among these logic modules is achieved using Actel’s
patented
metal-to-metal
programmable
antifuse
interconnect elements. The antifuse interconnect is
made up of a combination of amorphous silicon and
dielectric material with barrier metals and has an "on"
state resistance of 25Ω with a capacitance of 1.0fF for
low-signal impedance. The antifuses are normally open
circuit and, when programmed, form a permanent low-
S0
Routed
Data Input S1
PSET
DirectConnect
Input
D
Q
Y
HCLK
CLKA,
CLKB,
Internal Logic
CKS
Figure 1-1 •
R-Cell
CLR
CKP
v4.3
1-1
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