CY7C342B-30JCR datasheet, PDF - EEWORLD Datasheet

CY7C342B-30JCR: DescriptionOT PLD, 60ns, CMOS, PQCC68, PLASTIC, LCC-68; CategoryProgrammable logic devices Programmable logic; File Size618KB，17 Pages; ManufacturerCypress Semiconductor

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CY7C342B-30JCR Overview

OT PLD, 60ns, CMOS, PQCC68, PLASTIC, LCC-68

Parameter Name	Attribute value
Maker	Cypress Semiconductor
Parts packaging code	LCC
package instruction	QCCJ,
Contacts	68
Reach Compliance Code	unknown
Other features	LABS INTERCONNECTED BY PIA; 8 LABS; 128 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK
maximum clock frequency	27.7 MHz
JESD-30 code	S-PQCC-J68
length	24.2316 mm
Dedicated input times	7
Number of I/O lines	52
Number of terminals	68
Maximum operating temperature	70 °C
Minimum operating temperature
organize	7 DEDICATED INPUTS, 52 I/O
Output function	MACROCELL
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Package shape	SQUARE
Package form	CHIP CARRIER
Programmable logic type	OT PLD
propagation delay	60 ns
Certification status	Not Qualified
Maximum seat height	5.08 mm
Maximum supply voltage	5.25 V
Minimum supply voltage	4.75 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
width	24.2316 mm

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