a
FEATURES
Performance
13.3 ns Instruction Cycle Time @ 2.5 V (Internal),
75 MIPS Sustained Performance
Single-Cycle Instruction Execution
Single-Cycle Context Switch
3-Bus Architecture Allows Dual Operand Fetches in
Every Instruction Cycle
Multifunction Instructions
Power-Down Mode Featuring Low CMOS Standby Power
Dissipation with 200 CLKIN Cycle Recovery from
Power-Down Condition
Low Power Dissipation in Idle Mode
DSP
Microcomputer
ADSP-2185M
System Interface
Flexible I/O Structure Allows 2.5 V or 3.3 V Operation;
All Inputs Tolerate up to 3.6 V Regardless of Mode
16-Bit Internal DMA Port for High-Speed Access to
On-Chip Memory (Mode Selectable)
4 MByte Memory Interface for Storage of Data Tables
and Program Overlays (Mode Selectable)
8-Bit DMA to Byte Memory for Transparent Program
and Data Memory Transfers (Mode Selectable)
I/O Memory Interface with 2048 Locations Supports
Parallel Peripherals (Mode Selectable)
Programmable Memory Strobe and Separate I/O
Memory Space Permits “Glueless” System Design
Programmable Wait State Generation
Two Double-Buffered Serial Ports with Companding
Hardware and Automatic Data Buffering
Automatic Booting of On-Chip Program Memory from
Byte-Wide External Memory, e.g., EPROM, or
through Internal DMA Port
Six External Interrupts
13 Programmable Flag Pins Provide Flexible System
Signaling
UART Emulation through Software SPORT Reconfiguration
ICE-Port™ Emulator Interface Supports Debugging in
Final Systems
Integration
ADSP-2100 Family Code Compatible (Easy to Use
Algebraic Syntax), with Instruction Set Extensions
80K Bytes of On-Chip RAM, Configured as
16K Words Program Memory RAM
16K Words Data Memory RAM
Dual-Purpose Program Memory for Both Instruction and
Data Storage
Independent ALU, Multiplier/Accumulator, and Barrel
Shifter Computational Units
Two Independent Data Address Generators
Powerful Program Sequencer Provides Zero Overhead
Looping Conditional Instruction Execution
Programmable 16-Bit Interval Timer with Prescaler
100-Lead LQFP and 144-Ball Mini-BGA
FUNCTIONAL BLOCK DIAGRAM
POWER-DOWN
CONTROL
MEMORY
DATA ADDRESS
GENERATORS
DAG1
DAG2
PROGRAM
SEQUENCER
PROGRAM
MEMORY
16K 24 BIT
DATA
MEMORY
16K
16 BIT
PROGRAMMABLE
I/O
AND
FLAGS
FULL MEMORY MODE
EXTERNAL
ADDRESS
BUS
EXTERNAL
DATA
BUS
BYTE DMA
CONTROLLER
OR
DATA MEMORY DATA
EXTERNAL
DATA
BUS
INTERNAL
DMA
PORT
HOST MODE
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
ARITHMETIC UNITS
ALU
MAC
SHIFTER
SERIAL PORTS
SPORT0
SPORT1
TIMER
ADSP-2100 BASE
ARCHITECTURE
ICE-Port is a trademark of Analog Devices, Inc.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000
ADSP-2185M* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS
View a parametric search of comparable parts.
DOCUMENTATION
Application Notes
•
AN-227: Digital Control System Design with the
ADSP-2100 Family
•
AN-227: Digital Control System Design with the
ADSP-2100 Family
•
AN-334: Digital Signal Processing Techniques
•
AN-524: ADV601/ADV611 Bin Width Calculation in
ADSP-21xx DSP
•
EE-06: ADSP-21xx Serial Port Startup Issues
•
EE-100: ADSP-218x External Overlay Memory
•
EE-102: Mode D and ADSP-218x Pin Compatibility - the
FAQs
•
EE-103: Performing Level Conversion Between 5v and 3.3v
IC's
•
EE-104: Setting Up Streams with the VisualDSP Debugger
•
EE-11: ADSP-2181 Priority Chain & IDMA Holdoffs
•
EE-115: ADSP-2189 IDMA Interface to Motorola MC68300
Family of Microprocessors
•
EE-12: Interrupts and Programmable Flags on the
ADSP-2185/2186
•
EE-121: Porting Code from ADSP-21xx to ADSP-219x
•
EE-122: Coding for Performance on the ADSP-219x
•
EE-123: An Overview of the ADSP-219x Pipeline
•
EE-124: Booting up the ADSP-2192
•
EE-125: ADSP-218x Embedded System Software
Management and In-System-Programming (ISP)
•
EE-128: DSP in C++: Calling Assembly Class Member
Functions From C++
•
EE-129: ADSP-2192 Interprocessor Communication
•
EE-130: Making Fast Transition from ADSP-21xx to
ADSP-219x
•
EE-131: Booting the ADSP-2191/95/96 DSPs
•
EE-133: Converting From Legacy Architecture Files To
Linker Description Files for the ADSP-218x
•
EE-139: Interfacing the ADSP-2191 to an AD7476 via the
SPI Port
•
EE-142: Autobuffering, C and FFTs on the ADSP-218x
•
EE-144: Creating a Master-Slave SPI Interface Between
Two ADSP-2191 DSPs
•
EE-145: SPI Booting of the ADSP-2191 using the Atmel
AD25020N on an EZ-KIT Lite Evaluation Board
•
EE-146: Implementing a Boot Manager for ADSP-218x
Family DSPs
•
EE-152: Using Software Overlays with the ADSP-219x and
VisualDSP 2.0++
•
EE-153: ADSP-2191 Programmable PLL
•
EE-154: ADSP-2191 Host Port Interface
•
EE-156: Support for the H.100 protocol on the ADSP-2191
•
EE-158: ADSP-2181 EZ-Kit Lite IDMA to PC Printer Port
Interface
•
EE-159: Initializing DSP System & Control Registers From C
and C++
•
EE-164: Advanced EPROM Boot and No-boot Scenarios
with ADSP-219x DSPs
•
EE-168: Using Third Overtone Crystals with the ADSP-218x
DSP
•
EE-17: ADSP-2187L Memory Organization
•
EE-18: Choosing and Using FFTs for ADSP-21xx
•
EE-188: Using C To Implement Interrupt-Driven Systems
On ADSP-219x DSPs
•
EE-2: Using ADSP-218x I/O Space
•
EE-226: ADSP-2191 DSP Host Port Booting
•
EE-227: CAN Configuration Procedure for ADSP-21992
DSPs
•
EE-249: Implementing Software Overlays on ADSP-218x
DSPs with VisualDSP++®
•
EE-32: Language Extensions: Memory Storage Types, ASM
& Inline Constructs
•
EE-33: Programming The ADSP-21xx Timer In C
•
EE-35: Troubleshooting your ADSP-218x EZ-ICE
•
EE-356: Emulator and Evaluation Hardware
Troubleshooting Guide for CCES Users
•
EE-36: ADSP-21xx Interface to the IOM-2 bus
•
EE-38: ADSP-2181 IDMA Port - Cycle Steal Timing
•
EE-39: Interfacing 5V Flash Memory to an ADSP-218x (Byte
Programming Algorithm)
•
EE-48: Converting Legacy 21xx Systems To A 218x System
Design
•
EE-5: ADSP-218x Full Memory Mode vs. Host Memory
Mode
•
EE-60: Simulating an RS-232 UART Using the Synchronous
Serial Ports on the ADSP-21xx Family DSPs
•
EE-64: Setting Mode Pins on Reset
•
EE-71: Minimum Rise Time Specs for Critical Interrupt and
Clock Signals on the ADSP-21x1/21x5
•
EE-74: Analog Devices Serial Port Development and
Troubleshooting Guide
•
EE-78: BDMA Usage on 100 pin ADSP-218x DSPs
Configured for IDMA Use
•
EE-79: EPROM Booting In Host Mode with 100 Pin 218x
Processors
•
EE-82: Using an ADSP-2181 DSP's IO Space to IDMA Boot
Another ADSP-2181
•
EE-89: Implementing A Software UART on the ADSP-2181
EZ-Kit-Lite
•
EE-90: Using the 21xx C-FFT Library
•
EE-96: Interfacing Two AD73311 Codecs to the ADSP-218x
Data Sheet
•
ADSP-2185M: 16-bit, 75 MIPS, 2.5v, 2 serial ports, host
port, 80 KB RAM Data Sheet
Integrated Circuit Anomalies
•
ADSP-2185M Anomaly List for Revision 2.1
Processor Manuals
•
ADSP 21xx Processors: Manuals
•
ADSP-218x DSP Hardware Reference
•
ADSP-218x DSP Instruction Set Reference
•
Using the ADSP-2100 Family Volume 2
Software Manuals
•
VisualDSP++ 3.5 Assembler and Preprocessor Manual for
ADSP-218x and ADSP-219x DSPs
•
VisualDSP++ 3.5 C Compiler and Library Manual for
ADSP-218x DSPs
•
VisualDSP++ 3.5 C/C++ Compiler and Library Manual for
ADSP-219x Processors
•
VisualDSP++ 3.5 Linker and Utilities Manual for 16-Bit
Processors
•
VisualDSP++ 3.5 Loader Manual for 16-Bit Processors
SOFTWARE AND SYSTEMS REQUIREMENTS
•
Software and Tools Anomalies Search
TOOLS AND SIMULATIONS
•
ADSP-218xM IBIS Datafile (LQFP Package)
REFERENCE MATERIALS
Product Selection Guide
•
ADI Complementary Parts Guide - Supervisory Devices
and DSP Processors
DESIGN RESOURCES
•
ADSP-2185M Material Declaration
•
PCN-PDN Information
•
Quality And Reliability
•
Symbols and Footprints
SAMPLE AND BUY
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TECHNICAL SUPPORT
Submit a technical question or find your regional support
number.
DISCUSSIONS
View all ADSP-2185M EngineerZone Discussions.
DOCUMENT FEEDBACK
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ADSP-2185M
TABLE OF CONTENTS
FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . 1
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 3
DEVELOPMENT SYSTEM . . . . . . . . . . . . . . . . . . . . . . . 3
Additional Information . . . . . . . . . . . . . . . . . . . . . . . . . . 3
ARCHITECTURE OVERVIEW . . . . . . . . . . . . . . . . . . . . 4
Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Common-Mode Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Memory Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Full Memory Mode Pins (Mode C = 0) . . . . . . . . . . . . . . 7
Host Mode Pins (Mode C = 1) . . . . . . . . . . . . . . . . . . . . 7
Terminating Unused Pins . . . . . . . . . . . . . . . . . . . . . . . . 8
Pin Terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
LOW POWER OPERATION . . . . . . . . . . . . . . . . . . . . . . . 9
Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Idle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Slow Idle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
SYSTEM INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
RESET
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
MODES OF OPERATION . . . . . . . . . . . . . . . . . . . . . . . 11
Setting Memory Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Passive Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Active Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
IACK
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
MEMORY ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . 12
Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Memory Mapped Registers (New to the
ADSP-2185M) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
I/O Space (Full Memory Mode) . . . . . . . . . . . . . . . . . . . 13
Composite Memory Select (CMS) . . . . . . . . . . . . . . . . . 14
Byte Memory Select (BMS) . . . . . . . . . . . . . . . . . . . . . . 14
Byte Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Byte Memory DMA (BDMA, Full Memory Mode) . . . . 14
Internal Memory DMA Port
(IDMA Port; Host Memory Mode) . . . . . . . . . . . . . . 15
Bootstrap Loading (Booting) . . . . . . . . . . . . . . . . . . . . . 15
IDMA Port Booting . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Bus Request and Bus Grant . . . . . . . . . . . . . . . . . . . . . . 16
Flag I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Instruction Set Description . . . . . . . . . . . . . . . . . . . . . . 16
DESIGNING AN EZ-ICE-COMPATIBLE SYSTEM . . . 16
Target Board Connector for EZ-ICE Probe . . . . . . . . . . 17
Target Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . 17
PM, DM, BM, IOM, AND CM . . . . . . . . . . . . . . . . . . . . 17
Target System Interface Signals . . . . . . . . . . . . . . . . . . . 17
RECOMMENDED OPERATING CONDITIONS . . . . .
ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . .
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . .
TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . .
GENERAL NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TIMING NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MEMORY TIMING SPECIFICATIONS . . . . . . . . . . . .
FREQUENCY DEPENDENCY FOR
TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . .
ENVIRONMENTAL CONDITIONS . . . . . . . . . . . . . . .
POWER DISSIPATION . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Drive Currents . . . . . . . . . . . . . . . . . . . . . . . . . .
Capacitive Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TEST CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Disable Time . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Enable Time . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Signals and Reset . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupts and Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bus Request–Bus Grant . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IDMA Address Latch . . . . . . . . . . . . . . . . . . . . . . . . . . .
IDMA Write, Short Write Cycle . . . . . . . . . . . . . . . . . .
IDMA Write, Long Write Cycle . . . . . . . . . . . . . . . . . . .
IDMA Read, Long Read Cycle . . . . . . . . . . . . . . . . . . .
IDMA Read, Short Read Cycle . . . . . . . . . . . . . . . . . . .
IDMA Read, Short Read Cycle in Short Read
Only Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
100-LEAD LQFP PIN CONFIGURATION . . . . . . . . . .
LQFP Package Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . .
144-Ball Mini-BGA Package Pinout . . . . . . . . . . . . . . . . .
Mini-BGA Package Pinout . . . . . . . . . . . . . . . . . . . . . . . .
OUTLINE DIMENSIONS
100-Lead Metric Thin Plastic Quad Flatpack
(LQFP) (ST-100) . . . . . . . . . . . . . . . . . . . . . . . . . . .
OUTLINE DIMENSIONS
144-Ball Mini-BGA (CA-144) . . . . . . . . . . . . . . . . . . . .
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tables
18
18
19
19
19
19
19
20
20
20
20
21
22
22
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
40
Table I. Interrupt Priority and Interrupt
Vector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table II. Modes of Operation . . . . . . . . . . . . . . . . . . . . . . 11
Table III. PMOVLAY Bits . . . . . . . . . . . . . . . . . . . . . . . . 12
Table IV. DMOVLAY Bits . . . . . . . . . . . . . . . . . . . . . . . . 13
Table V. Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table VI. Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . 14
–2–
REV. 0
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