DM54LS20J datasheet, PDF - EEWORLD Datasheet

DM54LS20J: DescriptionDual 4-Input NAND Gates; Categorylogic logic; File Size124KB，6 Pages; ManufacturerNational Semiconductor（TI ）; Websitehttp://www.ti.com

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DM54LS20J Overview

Dual 4-Input NAND Gates

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
package instruction	DIP, DIP14,.3
Reach Compliance Code	unknow
series	LS
JESD-30 code	R-GDIP-T14
JESD-609 code	e0
length	19.43 mm
Load capacitance (CL)	50 pF
Logic integrated circuit type	NAND GATE
MaximumI(ol)	0.004 A
Number of functions	2
Number of entries	4
Number of terminals	14
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Package body material	CERAMIC, GLASS-SEALED
encapsulated code	DIP
Encapsulate equivalent code	DIP14,.3
Package shape	RECTANGULAR
Package form	IN-LINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Maximum supply current (ICC)	2.2 mA
Prop。Delay @ Nom-Su	15 ns
propagation delay (tpd)	15 ns
Certification status	Not Qualified
Schmitt trigger	NO
Maximum seat height	5.08 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	TTL
Temperature level	MILITARY
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	7.62 mm
Base Number Matches	1

	DM54LS20J	74LS20	DM54LS20W	DM74LS20M	DM74LS20N	54LS20LMQB	54LS20FMQB	54LS20DMQB	54LS20
Description	Dual 4-Input NAND Gates	Dual 4-Input NAND Gates	Dual 4-Input NAND Gates	Dual 4-Input NAND Gates	Dual 4-Input NAND Gates	Dual 4-Input NAND Gates	Dual 4-Input NAND Gates	Dual 4-Input NAND Gates	Dual 4-Input NAND Gates

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