V826516K04SATG-75 datasheet, PDF

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V826516K04SATG-75: DescriptionDDR DRAM Module, 16MX64, 0.75ns, CMOS, DIMM-184; Categorystorage storage; File Size86KB，13 Pages; ManufacturerMosel Vitelic Corporation ( MVC ); Websitehttp://www.moselvitelic.com

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V826516K04SATG-75 Overview

DDR DRAM Module, 16MX64, 0.75ns, CMOS, DIMM-184

V826516K04SATG-75 Parametric

Parameter Name	Attribute value
Maker	Mosel Vitelic Corporation ( MVC )
Parts packaging code	DIMM
package instruction	DIMM, DIMM184
Contacts	184
Reach Compliance Code	unknow
ECCN code	EAR99
access mode	SINGLE BANK PAGE BURST
Maximum access time	0.75 ns
Other features	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	133 MHz
I/O type	COMMON
JESD-30 code	R-XDMA-N184
memory density	1073741824 bi
Memory IC Type	DDR DRAM MODULE
memory width	64
Number of functions	1
Number of ports	1
Number of terminals	184
word count	16777216 words
character code	16000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	16MX64
Output characteristics	3-STATE
Package body material	UNSPECIFIED
encapsulated code	DIMM
Encapsulate equivalent code	DIMM184
Package shape	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY
power supply	2.5 V
Certification status	Not Qualified
refresh cycle	4096
self refresh	YES
Maximum standby current	0.2 A
Maximum slew rate	2.24 mA
Maximum supply voltage (Vsup)	2.7 V
Minimum supply voltage (Vsup)	2.3 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	NO LEAD
Terminal pitch	1.27 mm
Terminal location	DUAL

V826516K04SATG-75 Preview

MOSEL VITELIC

V826516K04SATG

2.5 VOLT 16M x 64 HIGH PERFORMANCE

UNBUFFERED DDR SDRAM MODULE

PRELIMINARY

Features

184 Pin Unbuffered 16,777,216 x 64 bit

Organization DDR SDRAM Modules

Utilizes High Performance 16M x 8 SDRAM in

TSOPII-66 Packages

Single +2.5V (± 0.2V) Power Supply

Programmable CAS Latency, Burst Length, and

Wrap Sequence (Sequential & Interleave)

Auto Refresh (CBR) and Self Refresh

All Inputs, Outputs are SSTL-2 Compatible

4096 Refresh Cycles every 64 ms

Serial Present Detect (SPD)

DDR SDRAM Performance

Component Used

Clock Frequency

(max.)

Clock Access Time

CAS Latency = 2.5

Description

The V826516K04SATG memory module is

organized 16,777,216 x 64 bits in a 184 pin memory

module. The 16M x 64 memory module uses 8

Mosel-Vitelic 16M x 8 DDR SDRAM. The x64

modules are ideal for use in high performance

computer systems where increased memory

density and fast access times are required.

-7

143

-75

133

-8

125

Units

MHz

(PC266A) (PC266B) (PC200)

V826516K04SATG Rev. 1.0 April 2001

MOSEL VITELIC

Part Number Information

MOSEL-VITELIC

MANUFACTURED

DDR

TSOP

2.5V

WIDTH

DEPTH

184 PIN UNBUFFERED

DIMM X 8 COMPONENT

SSTL-2

4 BANKS

REFRESH

RATE 4K

V826516K04SATG

-75

133 MHz

(PC133)

GOLD

Component Rev

Block Diagram

CS0

DQS0

DM0

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQS1

DM1

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQS2

DM2

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQS3

DM3

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

DQS

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

DQS

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQS7

DM7

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

DQS

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

DQS

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DQS6

DM6

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

DQS

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

DQS

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DQS5

DM5

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

DQS

DQS4

DM4

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

DQS

Clock Input

CK0/CK0

CK1/CK1

CK2/CK2

Clock Wiring

SDRAMs

2 SDRAMs

3 SDRAMs

Serial PD

BA0-BA1

A0 - A13

RAS

CAS

CKE0

BA0-BA1 : SDRAMs D0 - D7

A0 - A13 : SDRAMs D0 - D7

RAS : SDRAMs D0 - D7

CAS : SDRAMs D0 - D7

CKE : SDRAMs D0 - D7

WE : SDRAMs D0 - D7

SA0

SA1

SA2

SCL

SDA

DDQ

REF

DDID

0.1uF 0.1uF

0.1uF

D0 - D7

Strap: see Note 4

Notes:

1. DQ-to-I/O wiring is shown as recommended

but may be changed.

2. DQ/DQS/DM/CKE/CS relationships must be

maintained as shown.

3. DQ,DQS, DM/DQS resistors : 22 Ohms.

4. VDDID strap connections

(for memory device VDD, VDDQ) :

STRAP OUT (OPEN): VDD=VDDQ

STRAP IN (

): VDD≠VDDQ

V826516K04SATG Rev. 1.0 April 2001

MOSEL VITELIC

Pin Configurations (Front Side/Back Side)

Front

VREF

DQ0

VSS

DQ1

DQS0

DQ2

VDD

DQ3

VSS

DQ8

DQ9

DQS1

VDDQ

CK1

VSS

DQ10

DQ11

CKE0

VDDQ

DQ16

DQ17

DQS2

VSS

DQ18

VDDQ

DQ19

Front

DQ24

VSS

DQ25

DQS3

VDD

DQ26

DQ27

Vss

CB0*

CB1*

VDD

DQS8*

CB2*

VSS

CB3*

BA1

Key Key

DQ32

VDDQ

DQ33

DQS4

DQ34

VSS

BA0

DQ35

DQ40

Front

VDDQ

DQ41

CAS

VSS

DQS5

DQ42

DQ43

VDD

DQ48

DQ49

VSS

CK2

VDDQ

DQS6

DQ50

DQ51

VSS

VDDID

DQ56

DQ57

VDD

DQS7

DQ58

DQ59

VSS

SDA

SCL

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

Back

VSS

DQ4

DQ5

VDDQ

DM0

DQ6

DQ7

VSS

A13*

VDDQ

DQ12

DQ13

DM1

VDD

DQ14

DQ15

CKE1

VDDQ

BA2*

DQ20

A12*

VSS

DQ21

A11

DM2

VDD

DQ22

DQ23

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

V826516K04SATG

Back

VSS

DQ28

DQ29

VDDQ

DM3

DQ30

VSS

DQ31

CB4*

CB5*

VDDQ

CK0*

VSS

DM8*

A10

CB6*

VDDQ

CB7*

Key key

VSS

DQ36

DQ37

VDD

DM4

DQ38

DQ39

VSS

DQ44

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

Back

RAS

DQ45

VDDQ

CS0

CS1

DM5

VSS

DQ46

DQ47

VDDQ

DQ52

DQ53

VDD

DM6

DQ54

DQ55

VDDQ

DQ60

DQ61

VSS

DM7

DQ62

DQ63

VDDQ

SA0

SA1

SA2

VDDSPD

Notes:

These pins are not used in this module.

Pin Names

CK1, CK1, CK2, CK2

CS0

CKE0

RAS, CAS, WE

A0 ~ A11

BA0, BA1

DQ0~DQ63

DQS0~DQS7

DM0~DM7

VDD

Pin Description

Differential Clock Inputs

Chip Select Input

Clock Enable Input

Commend Sets Inputs

Address

Bank Address

Data Inputs/Outputs

Data Strobe Inputs/Outputs

Data-in Mask

Power Supply

VDDQ

VSS

VREF

VDDSPD

SA0~SA2

SCL

SDA

VDDID

Pin Description

DQs Power Supply

Ground

Reference Power Supply

Power Supply for SPD

PROM Address Inputs

PROM Clock

PROM Data I/O

VDD Identification Flag

Do not Use

No Connection

V826516K04SATG Rev. 1.0 April 2001

MOSEL VITELIC

Serial Presence Detect Information

Bin Sort:

A (PC266A @ CL = 2)

B (PC266B @ CL = 2.5)

C (PC200 @ CL = 2)

V826516K04SATG

Function Supported

Byte #

Hex value

80h

08h

07h

0Ch

0Ah

01h

40h

00h

04h

Function described

Defines # of Bytes written into serial memory at module manufacturer

Total # of Bytes of SPD memory device

Fundamental memory type

# of row address on this assembly

# of column address on this assembly

# of module Rows on this assembly

Data width of this assembly

.........Data width of this assembly

VDDQ and interface standard of this assembly

DDR SDRAM cycle time at CAS Latency =2.5

DDR SDRAM Access time from clock at CL=2.5

DIMM configuration type(Non-parity, Parity, ECC)

Refresh rate & type

Primary DDR SDRAM width

Error checking DDR SDRAM data width

Minimum clock delay for back-to-back random column

address

DDR SDRAM device attributes : Burst lengths supported

DDR SDRAM device attributes : # of banks on each DDR SDRAM

DDR SDRAM device attributes : CAS Latency supported

DDR SDRAM device attributes : CS Latency

DDR SDRAM device attributes : WE Latency

DDR SDRAM module attributes

128bytes

256bytes

SDRAM DDR

1 Bank

64 bits

SSTL 2.5V

8ns

7.5ns

7ns

80h

75h

00h

80h

08h

00h

01h

70h

75h

±0.8ns ±0.75n ±0.75n

Non-parity, ECC

15.6us & Self refresh

N/A

CCD

=1CLK

2,4,8

4 banks

2,2.5

0CLK

1CLK

Registered address&

control inputs and On-card

DLL

+/-0.2V voltage tolerance

10ns

7.5ns

±0.75

20ns

15ns

0Eh

04h

0Ch

01h

02h

20h

DDR SDRAM device attributes : General

DDR SDRAM cycle time at CL =2

DDR SDRAM Access time from clock at CL =2

DDR SDRAM cycle time at CL =1.5

DDR SDRAM Access time from clock at CL =1.5

Minimum row precharge time (=t

)

Minimum row activate to row active delay(=t

RRD

)

00h

A0h

80h

A0h

75h

00h

50h

3Ch

50h

3Ch

50h

3Ch

75h

±0.8ns ±0.75n

20ns

15ns

20ns

15ns

V826516K04SATG Rev. 1.0 April 2001

MOSEL VITELIC

Serial Presence Detect Information (cont.)

V826516K04SATG

Function Supported

Byte #

36-61

65 -71

73-90

95~98

Hex value

50h

30h

Function described

Minimum RAS to CAS delay(=t

RCD

)

Minimum active to precharge time(=t

RAS

)

Module ROW density

Command and address signal input setup time

Command and address signal input hold time

Data signal input setup time

Data signal input hold time

Superset information (may be used in future)

SPD data revision code

Checksum for Bytes 0 ~ 62

Manufacturer JEDEC ID code

....... Manufacturer JEDEC ID code

Manufacturing location

Module part number (ASCII)

Manufacturer revison code (For PCB)

Manufacturer revison code (For component)

Manufacturing date (Week)

Manufacturing date (Year)

Assembly serial #

20ns

48ns

20ns

48ns

64MB

20ns

45ns

50h

30h

10h

50h

2Dh

1.1ns

0.6ns

0.9ns

0.5ns

0.9ns

0.5ns

B0h

60h

90h

50h

00h

90h

50h

Initial release

Mosel Vitelic

20h

9Fh

40h

01h

6Ch

V826516K04SATG

Undefined

00h

99~127 Manufacturer specific data (may be used in future)

128~255 Open for customer use

V826516K04SATG Rev. 1.0 April 2001

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V826516K04SATG-75 Related Products

	V826516K04SATG-75	V826516K04SATG-7	V826516K04SATG-8
Description	DDR DRAM Module, 16MX64, 0.75ns, CMOS, DIMM-184	DDR DRAM Module, 16MX64, 0.75ns, CMOS, DIMM-184	DDR DRAM Module, 16MX64, 0.8ns, CMOS, DIMM-184
Maker	Mosel Vitelic Corporation ( MVC )	Mosel Vitelic Corporation ( MVC )	Mosel Vitelic Corporation ( MVC )
Parts packaging code	DIMM	DIMM	DIMM
package instruction	DIMM, DIMM184	DIMM, DIMM184	DIMM, DIMM184
Contacts	184	184	184
Reach Compliance Code	unknow	unknown	unknown
ECCN code	EAR99	EAR99	EAR99
access mode	SINGLE BANK PAGE BURST	SINGLE BANK PAGE BURST	SINGLE BANK PAGE BURST
Maximum access time	0.75 ns	0.75 ns	0.8 ns
Other features	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	133 MHz	143 MHz	125 MHz
I/O type	COMMON	COMMON	COMMON
JESD-30 code	R-XDMA-N184	R-XDMA-N184	R-XDMA-N184
memory density	1073741824 bi	1073741824 bit	1073741824 bit
Memory IC Type	DDR DRAM MODULE	DDR DRAM MODULE	DDR DRAM MODULE
memory width	64	64	64
Number of functions	1	1	1
Number of ports	1	1	1
Number of terminals	184	184	184
word count	16777216 words	16777216 words	16777216 words
character code	16000000	16000000	16000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	70 °C	70 °C	70 °C
organize	16MX64	16MX64	16MX64
Output characteristics	3-STATE	3-STATE	3-STATE
Package body material	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED
encapsulated code	DIMM	DIMM	DIMM
Encapsulate equivalent code	DIMM184	DIMM184	DIMM184
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY
power supply	2.5 V	2.5 V	2.5 V
Certification status	Not Qualified	Not Qualified	Not Qualified
refresh cycle	4096	4096	4096
self refresh	YES	YES	YES
Maximum standby current	0.2 A	0.2 A	0.184 A
Maximum slew rate	2.24 mA	2.24 mA	2.2 mA
Maximum supply voltage (Vsup)	2.7 V	2.7 V	2.7 V
Minimum supply voltage (Vsup)	2.3 V	2.3 V	2.3 V
Nominal supply voltage (Vsup)	2.5 V	2.5 V	2.5 V
surface mount	NO	NO	NO
technology	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal form	NO LEAD	NO LEAD	NO LEAD
Terminal pitch	1.27 mm	1.27 mm	1.27 mm
Terminal location	DUAL	DUAL	DUAL

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Shortcut: 00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

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