UT54ACS162245SUCA datasheet, PDF

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UT54ACS162245SUCA: DescriptionBus Transceiver, AC Series, 2-Func, 8-Bit, True Output, CMOS, CDFP48, 0.390 X 0.640 INCH, 0.025 INCH PITCH, DFP-48; Categorylogic logic; File Size172KB，13 Pages; ManufacturerCobham Semiconductor Solutions

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UT54ACS162245SUCA Overview

Bus Transceiver, AC Series, 2-Func, 8-Bit, True Output, CMOS, CDFP48, 0.390 X 0.640 INCH, 0.025 INCH PITCH, DFP-48

UT54ACS162245SUCA Parametric

Parameter Name	Attribute value
Maker	Cobham Semiconductor Solutions
Parts packaging code	DFP
package instruction	DFP,
Contacts	48
Reach Compliance Code	unknow
Other features	PORT B REQUIRES 3.3V VDD
series	AC
JESD-30 code	R-CDFP-F48
JESD-609 code	e0
length	15.875 mm
Logic integrated circuit type	BUS TRANSCEIVER
Number of digits	8
Number of functions	2
Number of ports	2
Number of terminals	48
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Output characteristics	3-STATE
Output polarity	TRUE
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	DFP
Package shape	RECTANGULAR
Package form	FLATPACK
propagation delay (tpd)	10 ns
Certification status	Not Qualified
Maximum seat height	3.048 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	2.3 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal surface	TIN LEAD
Terminal form	FLAT
Terminal pitch	0.635 mm
Terminal location	DUAL
width	9.652 mm

UT54ACS162245SUCA Preview

UT54ACS162245S

RadHard Schmitt CMOS 16-bit Bidirectional MultiPurpose

Low Voltage Transceiver

Datasheet

August 2006

FEATURES

•

Voltage translation

- 3.3V bus to 2.5V bus

- 2.5V bus to 3.3V bus

•

Cold sparing all pins

•

0.25µ Commercial RadHard

TM

CMOS

- Total dose: 300Krad(Si) and 1Mrad(Si)

- Single Event Latchup immune

•

High speed, low power consumption

•

Schmitt trigger inputs to filter noisy signals

•

Cold and Warm Spare - all outputs

•

Available QML Q or V processes

•

Standard Microcircuit Drawing 5962-02543

•

Package:

- 48-lead flatpack, 25 mil pitch (.390 x .640)

DESCRIPTION

The 16-bit wide UT54ACS162245S MultiPurpose low voltage

transceiver is built using Aeroflex UTMC’s Commercial

RadHard

TM

epitaxial CMOS technology and is ideal for space

applications. This high speed, low power UT54ACS162245S

low voltage transceiver is designed to perform multiple func-

tions including: asynchronous two-way communication,

Schmitt input buffering, voltage translation, warm and cold spar-

ing. With V

DD

equal to zero volts, the UT54ACS162245S out-

puts and inputs present a minimum impedance of 1MΩ making

it ideal for "cold spare" applications. Balanced outputs and low

"on" output impedance make the UT54ACS162245S well suited

for driving high capacitance loads and low impedance back-

planes. The UT54ACS162245S enables system designers to in-

terface 2.5 volt CMOS compatible components with 3.3 volt

CMOS components. For voltage translation, the A port interfac-

es with the 2.5 volt bus; the B port interfaces with the 3.3 volt

bus. The direction control (DIRx) controls the direction of data

flow. The output enable (OEx) overrides the direction control

and disables both ports. These signals can be driven from either

port A or B. The direction and output enable controls operate

these devices as either two independent 8-bit transceivers or one

16-bit transceiver.

LOGIC SYMBOL

OE1 (48)

OE2 (25)

(1)

DIR1

(47)

(46)

(44)

G1

G2

2EN1 (BA)

2EN2 (AB)

1EN1 (BA)

1EN2 (AB)

11

12

(24)

DIR2

1A1

1A2

1A3

(2)

(3)

(5)

(6)

(8)

1B1

1B2

1B3

1B4

(43)

1A4

(41)

1A5

(40)

1A6

(38)

1A7

(37)

1A8

(36)

2A1

2A2

2A3

(35)

(33)

21

22

1B5

(9)

1B6

(11)

1B7

(12)

1B8

(13)

2B1

(14)

2B2

(16)

2B3

(17)

2B4

(19)

2B5

(20)

2B6

(22)

2B7

(23)

2B8

(32)

2A4

(30)

2A5

(29)

2A6

(27)

2A7

(26)

2A8

PIN DESCRIPTION

Pin Names

OEx

DIRx

xAx

xBx

Description

Output Enable Input (Active Low)

Direction Control Inputs

Side A Inputs or 3-State Outputs (2.5V Port)

Side B Inputs or 3-State Outputs (3.3V Port)

1

PINOUTS

When V

DD2

is at 2.5 volts, either 2.5 or 3.3 volts CMOS logic

levels can be applied to all control inputs. For proper operation

connect power to all V

DD

and ground all V

SS

pins (i.e., no float-

ing V

DD

or V

SS

input pins). Tie unused inputs to V

SS

. Always

insure V

DD1

> V

DD2

during operation of the part.

48-Lead Flatpack

Top View

FUNCTION TABLE

OE1

1A1

1A2

V

SS

1A3

1A4

VDD2

1A5

1A6

V

SS

1A7

1A8

2A1

2A2

V

SS

2A3

2A4

VDD2

2A5

2A6

V

SS

2A7

2A8

OE2

ENABLE

OEx

L

H

DIRECTION

DIRx

L

H

X

OPERATION

B Data To A Bus

A Data To B Bus

Isolation

DIR1

1B1

1B2

V

SS

1B3

1B4

VDD1

1B5

1B6

V

SS

1B7

1B8

2B1

2B2

V

SS

2B3

2B4

VDD1

2B5

2B6

V

SS

2B7

2B8

DIR2

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

COLD/WARM SPARE FUNCTION

The device will place all outputs into a high-impedance state if

either V

DD

supply is taken to zero volts (I

WS

, warm spare), or

if both V

DD

supplies are set to zero volts (I

CS

, cold spare).

DEVICE POWER UP FUNCTION

The device will place all outputs into a high-impedance during

power-up. The high impedance state is maintained for a time

period approximately equal to the rise time of V

DD1

.

POWER TABLE

Port B

3.3 Volts

2.5 Volts

Port A

2.5 Volts

3.3 Volts

2.5 Volts

OPERATION

Voltage Translator

Non Translating

2

LOGIC DIAGRAM

DIR1

(1)

(48)

OE1

DIR2

(24)

(25)

OE2

1A1

(47)

(2)

1B1

2A1

(36)

(13)

2B1

1A2

(46)

(3)

1B2

2A2

(35)

(14)

2B2

1A3

(44)

(5)

1B3

2A3

(33)

(16)

2B3

3.3 V PORT

2.5V PORT

(6)

1A5

(41)

(8)

1A6

(40)

(9)

1A7

(38)

(11)

1A8

(37)

(12)

1B4

(17)

2A5

(30)

(19)

2A6

(29)

(20)

2A7

(27)

(22)

2A8

(26)

(23)

2B4

1B5

2B5

1B6

2B6

1B7

2B7

1B8

2B8

3

3.3 V PORT

1A4

(43)

2A4

(32)

RADIATION HARDNESS SPECIFICATIONS

1

PARAMETER

Total Dose

SEL Latchup

Neutron Fluence

(Note 2)

LIMIT

1.0E5

>113

1.0E14

UNITS

rad(Si)

MeV-cm

2

/mg

n/cm

2

Notes:

1. Logic will not latchup during radiation exposure within the limits defined in the table.

2. Not tested, inherent to CMOS technology.

ABSOLUTE MAXIMUM RATINGS

1

SYMBOL

V

I/O (Note 2)

V

DD1

V

DD2

T

STG

T

J (Note 3)

Θ

JC

I

P

D

PARAMETER

Voltage any pin

Supply voltage

Storage Temperature range

Maximum junction temperature

Thermal resistance junction to case

DC input current

Maximum power dissipation

LIMIT (Mil only)

-.3 to V

DD1

+.3

-0.3 to 4.0

-65 to +150

+150

20

±10

1

UNITS

V

°C

°C/W

mA

W

Note:

1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at

these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended

periods may affect device reliability and performance.

2. For Cold Spare mode (V

DD1

=VSS, V

DD2

=VSS), V

I/O

may be -0.3V to the maximum recommended operating level of V

DD1

+0.3V.

3. Maximum junction temperature may be increased to +175

o

C during burn-in and life test.

DUAL SUPPLY OPERATING CONDITIONS

SYMBOL

V

DD1

V

DD2

V

IN

T

C

PARAMETER

Supply voltage

Input voltage any pin

Temperature range

LIMIT

2.3 to 3.6

0 to V

DD1

-55 to + 125

UNITS

V

°C

4

DC ELECTRICAL CHARACTERISTICS

1

( -55°C < T

C

< +125°C)

SYMBOL

V

T

+

V

T

-

V

H1

V

H2

I

IN

PARAMETER

Schmitt Trigger, positive going threshold

2

CONDITION

V

DD

from 2.3 to 3.6

.3V

DD

0.5

0.4

-1

3

MIN

MAX

.7V

DD

UNIT

V

µA

Schmitt Trigger, negative going threshold

2

V

DD

from 2.3 to 3.6

Schmitt Trigger range of hysteresis

9

Schmitt Trigger range of hysteresis

9

Input leakage current

9

V

DD

from 3.0 to 3.6

V

DD

from 2.3 to 2.7

V

DD

from 2.7 to 3.6

V

IN

= V

DD

or V

SS

I

OZ

Three-state output leakage current

9

V

DD

from 2.7 to 3.6

V

IN

= V

DD

or V

SS

-1

3

µA

I

CS

Cold sparing input leakage current

3,11

V

IN

= 3.6

V

DD

= V

SS

-5

5

µA

I

WS

Warm sparing input leakage current

3,11

V

IN

= V

SS

or V

DD,

V

DD1

= 0,

V

DD2

= V

DD or

V

DD1 =

V

DD,

V

DD2

= 0

-5

5

µA

I

OS1

Short-circuit output current

5, 10

V

O

= V

DD

or V

SS

V

DD

from 3.0 to 3.6

-200

200

mA

I

OS2

Short-circuit output current

5, 10

V

O

= V

DD

or V

SS

V

DD

from 2.3 to 2.7

-100

100

mA

V

OL1

Low-level output voltage

9

I

OL

= 8mA

I

OL

= 100µA

V

DD

= 3.0

0.4

0.2

0.4

0.2

V

DD

- 0.7

V

DD

- 0.2

V

DD

- 0.7

V

DD

- 0.2

V

OL2

Low-level output voltage

9

I

OL

= 8mA

I

OL

= 100µA

V

DD

= 2.3

V

OH1

High-level output voltage

9

I

OH

= -8mA

I

OH

= -100µA

V

DD

= 3.0

V

OH2

High-level output voltage

9

I

OH

= -8mA

I

OH

= -100µA

V

DD

= 2.3

V

5

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UT54ACS162245SUCA Related Products

	UT54ACS162245SUCA	UT54ACS162245SUPC	UT54ACS162245SUCC
Description	Bus Transceiver, AC Series, 2-Func, 8-Bit, True Output, CMOS, CDFP48, 0.390 X 0.640 INCH, 0.025 INCH PITCH, DFP-48	Bus Transceiver, AC Series, 2-Func, 8-Bit, True Output, CMOS, CDFP48, 0.390 X 0.640 INCH, 0.025 INCH PITCH, DFP-48	Bus Transceiver, AC Series, 2-Func, 8-Bit, True Output, CMOS, CDFP48, 0.390 X 0.640 INCH, 0.025 INCH PITCH, DFP-48
Maker	Cobham Semiconductor Solutions	Cobham Semiconductor Solutions	Cobham Semiconductor Solutions
Parts packaging code	DFP	DFP	DFP
package instruction	DFP,	DFP,	DFP,
Contacts	48	48	48
Reach Compliance Code	unknow	unknown	unknown
Other features	PORT B REQUIRES 3.3V VDD	PORT B REQUIRES 3.3V VDD	PORT B REQUIRES 3.3V VDD
series	AC	AC	AC
JESD-30 code	R-CDFP-F48	R-CDFP-F48	R-CDFP-F48
JESD-609 code	e0	e4	e4
length	15.875 mm	15.875 mm	15.875 mm
Logic integrated circuit type	BUS TRANSCEIVER	BUS TRANSCEIVER	BUS TRANSCEIVER
Number of digits	8	8	8
Number of functions	2	2	2
Number of ports	2	2	2
Number of terminals	48	48	48
Output characteristics	3-STATE	3-STATE	3-STATE
Output polarity	TRUE	TRUE	TRUE
Package body material	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED
encapsulated code	DFP	DFP	DFP
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	FLATPACK	FLATPACK	FLATPACK
propagation delay (tpd)	10 ns	10 ns	10 ns
Certification status	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	3.048 mm	3.048 mm	3.048 mm
Maximum supply voltage (Vsup)	3.6 V	3.6 V	3.6 V
Minimum supply voltage (Vsup)	2.3 V	2.3 V	2.3 V
Nominal supply voltage (Vsup)	2.5 V	2.5 V	2.5 V
surface mount	YES	YES	YES
technology	CMOS	CMOS	CMOS
Terminal surface	TIN LEAD	GOLD	GOLD
Terminal form	FLAT	FLAT	FLAT
Terminal pitch	0.635 mm	0.635 mm	0.635 mm
Terminal location	DUAL	DUAL	DUAL
width	9.652 mm	9.652 mm	9.652 mm
Maximum operating temperature	125 °C	-	125 °C
Minimum operating temperature	-55 °C	-	-55 °C
Temperature level	MILITARY	-	MILITARY

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