PHT
Vishay Sfernice
High Precision Wraparound - High Temperature (230 °C)
Thin Film Chip Resistors
FEATURES
•
Operating temperature range:
- 55 °C; + 215 °C
•
Storage temperature: - 55 °C; + 230 °C
•
Gold terminations (< 1 µm thick)
•
4 sizes available (0603, 0805, 1206, 2010) -
other sizes upon request
INTRODUCTION
For applications such as down hole applications, the need for
parts able to withstand very severe conditions (temperature
as high as 215 °C powered or up to 230 °C un-powered) has
leaded Vishay Sfernice to push out the limit of the thin film
technology.
Designers might read the application note: Power
Dissipation Considerations in High Precision Vishay Sfernice
Thin Film Chip Resistors and Arrays (P, PRA etc…) (High
Temperature Application)
www.vishay.com/doc?53047
in
conjunction with this datasheet to help them to properly
design their PCBs and get the best performances of the PHT.
Vishay Sfernice R&D engineers will be willing to support any
customer design considerations.
•
Temperature coefficient down to 25 ppm
(- 55 °C; + 215 °C)
•
Tolerance down to 0.05 %
•
Load life stability: 0.5 % max after 1000 h at 215 °C
(ambient) at Pn
•
SMD wraparound
•
Compliant to RoHS directive 2002/95/EC
DIMENSIONS
in millimeters (inches)
A
D
D
C
B
E
E
A
CASE
SIZE
MAX. TOL.
+ 0.152 (+ 0.006)
MIN. TOL.
- 0.152 (- 0.006)
NOMINAL
0603
0805
1206
2010
1.52 (0.060)
1.91 (0.075)
3.06 (0.120)
5.08 (0.200)
B
MAX. TOL.
+ 0.127 (+ 0.005)
MIN. TOL.
- 0.127 (- 0.005)
NOMINAL
0.85 (0.033)
0.38 (0.015)
1.27 (0.050)
1.60 (0.063)
2.54 (0.100)
0.5 (0.02)
± 0.127 (0.005)
0.13 (0.005)
0.40 (0.016)
0.48 (0.019)
D/E
C
NOMINAL
TOLERANCE
** Please see document “Vishay Material Category Policy”:
www.vishay.com/doc?99902
www.vishay.com
1
For technical questions, contact:
sfer@vishay.com
Document Number: 53050
Revision: 10-Aug-10
PHT
High Precision Wraparound - High Temperature (230 °C)
Thin Film Chip Resistors
SUGGESTED LAND PATTERN
(to IPC-7351A)
Vishay Sfernice
G
min.
X
max.
Z
max.
DIMENSIONS (in millimeter)
CHIP SIZE
Z
max.
0603
0805
1206
2010
2.37
2.76
3.91
5.93
G
min.
0.35
0.74
1.85
3.71
X
max.
0.98
1.40
1.73
2.67
STANDARD ELECTRICAL SPECIFICATIONS
TEST
Series
Ohmic Range
(1)
Temperature Coefficient
(2)
Tolerance
Power Rating (Pn)
(3)
Operating Temperature Range
Limiting Voltage
(3)
Load Life Stability
Storage Temperature Range
Shelf Life Stability
Notes
(1)
Please refer to table 3 for TCR versus ohmic values
(2)
See table 2
(3)
See table 1
SPECIFICATIONS
0603, 0805, 1206, 2010
10R to 7M6 (depending on series)
25 ppm/°C, 50 ppm/°C, 100 ppm/°C
0.05 %, 0.1 %, 0.5 %, 1 %
12.5 mW to 100 mW
- 55 °C; + 215 °C
75 V to 300 V
0.50 %
- 55 °C; + 230 °C
0.7 % typ. (1 % max.)
8000 h/230 °C
1000 h/215 °C (ambient) at Pn
215 °C
- 55 °C; + 215 °C
CONDITIONS
Caution:
Performances obtained with following mounting conditions:
PCB: Polyimide
Solder paste: PbSnAg (93.5/5/1.5)
Document Number: 53050
Revision: 10-Aug-10
For technical questions, contact:
sfer@vishay.com
www.vishay.com
2
PHT
Vishay Sfernice
High Precision Wraparound - High Temperature (230 °C)
Thin Film Chip Resistors
TABLE 1
SIZE
0603
0805
1206
2010
POWER RATING
(1)
12.5 mW
20 mW
33 mW
100 mW
LIMITING VOLTAGE
75 V
150 V
200 V
300 V
Note
(1)
For power handling improvement, please refer to application note 53047: Power Dissipation Considerations in High Precision Vishay Sfernice
Thin Film Chip Resistors and Arrays (High Temperature Applications)
www.vishay.com/doc?/53047
and consult Vishay Sfernice
TABLE 2 - TEMPERATURE COEFFICIENT
Y
E
H
10 ppm/°C
25 ppm/°C
25 ppm/°C
50 ppm/°C
50 ppm/°C
100 ppm/°C
- 55 °C; + 155 °C
- 55 °C; + 215 °C
- 55 °C; + 155 °C
- 55 °C; + 215 °C
- 55 °C; + 155 °C
- 55 °C; + 215 °C
TABLE 3
OHMIC RANGE
(2)
SERIES
Min.
0603
0805
1206
2010
(2)
CT: Y
Max.
320K
511K
1M8
5M
Min.
10
Ω
10
Ω
10
Ω
10
Ω
39
Ω
39
Ω
39
Ω
39
Ω
CT: E/H
Max.
320K
725K
2M7
7M6
Note
Best tolerance possible:
0.5 %: 10
Ω
to < 20
Ω
0.1 %: 20
Ω
to < 39
Ω
0.05 %: 39
Ω
to max. value
PHT STABILITY CURVE
High Temperature Drift vs. Time
0.7
0.6
0.5
Drift in %
0.4
0.3
0.2
T = 185 °C
0.1
0.0
T = 230 °C
With
Pd
(T
j
= 230 °C)
T = 215 °C
T = 200 °C
0
1000
2000
3000
4000
Time in h
5000
6000
7000
8000
Note
• Stability will be dependent on resistivity of resistor. Above curves are worst case.
www.vishay.com
3
For technical questions, contact:
sfer@vishay.com
Document Number: 53050
Revision: 10-Aug-10
PHT
High Precision Wraparound - High Temperature (230 °C)
Thin Film Chip Resistors
MECHANICAL SPECIFICATIONS
Substrate
Resistive Element
Passivation
Protection
Terminations
Note
• For other terminations, please consult
Alumina
Nichrome (NiCr)
Silicon nitride (Si
3
N
4
)
Epoxy + Silicone
Gold (< 1 µm) over nickel barrier
Vishay Sfernice
POPULAR OPTIONS
It is recommended to consult Vishay Sfernice for availability first.
Option: Enlarged terminations:
For stringent and special power dissipation requirements, the thermal resistance between the resistive layer and the solder joint
can be reduced using enlarged terminations chip resistors which are soldered on large and thick copper pads acting as heatsink
(see application note: 53048 Power Dissipation in High Precision Vishay Sfernice Chip Resistors and Arrays (P Thin Film, PRA
Arrays, CHP Thick Film)
www.vishay.com/doc?53048.
Option to order: 0063 (applies to size 1206/2010).
DIMENSIONS
(Option 0063) in millimeters
Bottom view for mounting
A
Uncoated
ceramic
Enlarged
termination
B
F
D
E
A
CASE
SIZE
MAX. TOL.
+ 0.152
MIN. TOL.
- 0.152
NOMINAL
1206
2010
3.06
5.08
B
MAX. TOL.
+ 0.127
MIN. TOL.
- 0.127
NOMINAL
1.60
2.54
E
MAX. TOL.
+ 0.13
MIN. TOL.
- 0.13
NOMINAL
0.40
0.48
D
MAX. TOL.
+ 0.13
MIN. TOL.
- 0.13
NOMINAL
1.215
2.25
NOMINAL
0.63
F
MIN.
0.50
MAX.
0.76
SUGGESTED LAND PATTERN
(Option 0063)
G
min.
X
max.
Z
max.
CHIP SIZE
1206
2010
DIMENSIONS (in millimeter)
Z
max.
3.91
5.93
G
min.
0.50
X
max.
1.73
2.67
Document Number: 53050
Revision: 10-Aug-10
For technical questions, contact:
sfer@vishay.com
www.vishay.com
4
PHT
Vishay Sfernice
High Precision Wraparound - High Temperature (230 °C)
Thin Film Chip Resistors
PACKAGING
ESD packaging available: waffle-pack, and plastic tape and
reel (low conductivity). Paper tape available upon request
(ESD only).
NUMBER OF PIECES PER PACKAGE
SIZE MOQ
WAFFLE PACK
2" × 2"
TAPE AND REEL
MIN.
MAX.
TAPE
WIDTH
PACKAGING RULES
Waffle Pack
Can be filled up to maximum quantity indicated in the table
here above, taking into account the minimum order quantity.
When quantity ordered exceeds maximum quantity of a
single waffle pack, the waffle packs are stacked up on the top
of each other and closed by one single cover.
To get “not stacked up” waffle pack in case of ordered
quantity > maximum number of pieces per package:
Please consult Vishay Sfernice for specific ordering
code
Tape and Reel
Can be filled up to maximum quantity indicated in the table
here above, taking into account the minimum order quantity.
When quantity ordered is between the MOQ and the
maximum reel capacity, only one reel is provided.
When several reels are needed for ordered quantity
within MOQ and maximum reel capacity: Please consult
Vishay Sfernice for specific ordering code
0603
100
0805
100
1206
2010
Note
(1)
12 mm on request
140
60
2000
8 mm
(1)
100
4000
8 mm
GLOBAL PART NUMBER INFORMATION
Global Part Numbering: PHT1206Y1001BGT063
P
H
T
1
2
0
6
Y
1
0
0
1
B
G
T
0
6
3
GLOBAL
MODEL
PHT
SIZE
0603
0805
1206
2010
TCR
Y
E
H
VALUE
The first three digits
are significant figures
and the last digit
specifies the number
of zeros to follow, R
designates
decimal
point
10R0 = 10
Ω
3901 = 3900
Ω
1004 = 1 MΩ
TOLERANCE
W
= 0.05 %
B
= 0.1 %
D
= 0.5 %
F
=1%
TERMINATION
G
= Gold
N
= Tin/silver
(2)
PACKAGING
T
= Tape and reel
Blank
= Waffle pack
OPTION
Leave blank
if no option
Note
(2)
For usage at temperatures up to 200 °C maximum N (tin/silver termination are available upon request)
www.vishay.com
5
For technical questions, contact:
sfer@vishay.com
Document Number: 53050
Revision: 10-Aug-10
京公网安备 11010802033920号
EEWORLD
