P
Vishay Sfernice
High Precision Wraparound - Wide Ohmic Value Range
Thin Film Chip Resistors
FEATURES
•
Load life stability at ± 70 °C for 2000 h:
0.1 % under Pn/0.05 % under Pd
•
Low temperature coefficient down to
5 ppm/°C
(- 55 °C; + 155 °C)
•
Very low noise < 35 dB and
voltage coefficient
< 0.01 ppm/V
•
Wide resistance range: 10
Ω
to 50 MΩ
depending on size
•
Tolerances to
±
0.01 %
•
In lot tracking
≤
5 ppm/°C
•
Termination: thin film technology
•
Gold plated or pre-tinned terminations over nickel barrier
•
Short circuits (jumpers) r < 50 mR, I < 2 A
•
SMD wraparound terminations
•
Withstand moisture resistance test of AEC-Q200
•
Compliant to RoHS directive 2002/95/EC
For low noise and precision applications, superior stability,
low temperature coefficient of resistance, and low voltage
coefficient, Vishay Sfernice’s proven precision
thin film
wraparound
resistors
exceed
requirements
of
MIL-PRF-55342G characteristics Y ± 10 ppm/°C (- 55 °C;
+ 155 °C) down to ± 5 ppm/°C (- 55 °C; + 155 °C).
DIMENSIONS
in millimeters (inches)
A
D
D
C
B
E
E
A
CASE
SIZE
MAX. TOL.
+ 0.152 (+ 0.006)
MIN. TOL.
- 0.152 (- 0.006)
NOMINAL
0302
0402
0505
0603
0705/0805
1005
1206
1505
2010
0.75 (0.029)
1.00 (0.039)
1.27 (0.005)
1.52 (0.060)
1.91 (0.075)
2.54 (0.100)
3.06 (0.120)
3.81 (0.150)
5.08 (0.200)
B
MAX. TOL.
+ 0.127 (+ 0.005)
MIN. TOL.
- 0.127 (- 0.005)
NOMINAL
0.60 (0.024)
0.60 (0.024)
1.27 (0.050)
0.85 (0.033)
1.27 (0.050)
1.27 (0.050)
1.60 (0.063)
1.32 (0.052)
2.54 (0.100)
0.40 (0.016)
0.48 (0.019)
0.5 (0.02)
± 0.127 (0.005)
0.38 (0.015)
0.13 (0.005)
D/E
C
NOMINAL
0.15 (0.006)
0.25 (0.010)
TOLERANCE
0.08 (0.003)
0.1 (0.004)
Note
• Case size 2512 under development. Please consult Vishay Sfernice.
* Pb containing terminations are not RoHS compliant, exemptions may apply
** Please see document “Vishay Material Category Policy”:
www.vishay.com/doc?99902
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60
For technical questions, contact:
sfer@vishay.com
Document Number: 53017
Revision: 15-Mar-10
P
High Precision Wraparound - Wide Ohmic Value Range
Vishay Sfernice
Thin Film Chip Resistors
SUGGESTED LAND PATTERN
(to IPC-7351A)
G
min.
X
max.
Z
max.
DIMENSIONS
(in millimeter)
CHIP SIZE
Z
max.
0302
0402
0505
0603
0705/0805
1005
1206
1505
2010
1.30
1.55
1.82
2.37
2.76
3.39
3.91
4.66
5.93
G
min.
0.14
0.15
0.10
0.35
0.74
1.37
1.85
2.44
3.71
X
max.
0.73
0.73
1.40
0.98
1.40
1.40
1.73
1.45
2.67
Note
• Case size 2512 under development. Please consult Vishay Sfernice.
ELECTRICAL SPECIFICATIONS
CASE SIZE
POWER RATING
mW
Pn
(1)
0302
0402
0505
0603
0705/0805
1005
1206
1505
2010
40
63
125
125
200
250
330
350
1000
Pd
(1)
30
40
50
100
125
125
250
175
500
LIMITING ELEMENT VOLTAGE
V
25
50
50
75
150
75
200
75
300
RESISTANCE RANGE
(2)
10
Ω
to 500 kΩ
10
Ω
to 1.5 MΩ
10
Ω
to 4 MΩ
10
Ω
to 2.5 MΩ
10
Ω
to 10 MΩ
10
Ω
to 5 MΩ
10
Ω
to 35 MΩ
10
Ω
to 10 MΩ
10
Ω
to 50 MΩ
Notes
•
Case size 2512 under development. Please consult Vishay Sfernice.
(1)
Pn = Nominal power - Pd = Derated power intended to improve stability.
(2)
For ohmic range versus tolerance and TCR see detailed table page 62.
Document Number: 53017
Revision: 15-Mar-10
For technical questions, contact:
sfer@vishay.com
www.vishay.com
61
P
Vishay Sfernice
High Precision Wraparound - Wide Ohmic Value Range
Thin Film Chip Resistors
ELECTRICAL SPECIFICATIONS
Resistance Range:
Resistance Tolerance:
10
Ω
to 50 MΩ
± 0.1 % to ± 1 %
± 0.01 % to ± 0.05 % on Y type
Power Dissipation:
Pn:
40 mW to 1 W
Pd:
40 mW to 500 mW
on tolerance tighter than ± 0.05 %
Temperature Coefficient:
5 ppm (0 °C; 70 °C);
10 ppm (- 55 °C; + 155 °C)
TOLERANCE AND TCR VERSUS OHMIC VALUE
SIZE
VALUE
RANGE
10R to 500K
10R to 75K
39R to 75K
39R to 50K
100R to 50K
250R to 50K
10R to 1M5
10R to 150K
39R to 150K
39R to 100K
100R to 100K
250R to 100K
10R to 4M
10R to 300K
39R to 300K
39R to 260K
100R to 260K
250R to 260K
10R to 2M5
10R to 500K
39R to 500K
39R to 332K
100R to 332K
250R to 332K
10R to 10M
10R to 750K
39R to 750K
39R to 511K
100R to 511K
250R to 511K
10R to 5M
10R to 750K
39R to 750K
39R to 500K
100R to 500K
250R to 500K
10R to 35M
10R to 3M5
39R to 3M5
39R to 1M8
100R to 1M8
250R to 1M8
10R to 10M
10R to 1M
39R to 1M
39R to 750K
100R to 750K
250R to 750K
10R to 50M
10R to 6M
39R to 6M
39R to 3M
100R to 3M
250R to 3M
TIGHTEST
TOLERANCE
%
0.1
0.1
0.05
0.05
0.02
0.01
0.1
0.1
0.05
0.05
0.02
0.01
0.1
0.1
0.05
0.05
0.02
0.01
0.1
0.1
0.05
0.05
0.02
0.01
0.1
0.1
0.05
0.05
0.02
0.01
0.1
0.1
0.05
0.05
0.02
0.01
0.1
0.1
0.05
0.05
0.02
0.01
0.1
0.1
0.05
0.05
0.02
0.01
0.1
0.1
0.05
0.05
0.02
0.01
BEST TCR
(ppm/°C)
50
25
25
10 (5)
(3)
10 (5)
(3)
10 (5)
(3)
50
25
25
10 (5)
(3)
10 (5)
(3)
10 (5)
(3)
50
25
25
10 (5)
(3)
10 (5)
(3)
10 (5)
(3)
50
25
25
10 (5)
(3)
10 (5)
(3)
10 (5)
(3)
50
25
25
10 (5)
(3)
10 (5)
(3)
10 (5)
(3)
50
25
25
10 (5)
(3)
10 (5)
(3)
10 (5)
(3)
50
25
25
10 (5)
(3)
10 (5)
(3)
10 (5)
(3)
50
25
25
10 (5)
(3)
10 (5)
(3)
10 (5)
(3)
50
25
25
10 (5)
(3)
10 (5)
(3)
10 (5)
(3)
P0302
CLIMATIC SPECIFICATIONS
Operating Temp. Range:
- 55 °C to + 155 °C
For temperature up to 215 °C, please consult factory
P0402
MECHANICAL SPECIFICATIONS
Substrate:
Technology:
Film:
Protection:
Terminations:
Alumina
Thin film
Nickel chromium
with mineral
passivation or
CrSi
Silicone
B type:
SnPb over nickel barrier
for solder reflow
N type:
SnAg over nickel barrier
G type:
gold over nickel barrier
for other applications
P0505
P0603
TEMPERATURE COEFFICIENT
TCR
± 5 ppm/°C
(1)(2)
(2)
P0705/0805
FILM
NiCr
NiCr
NiCr
NiCr or CrSi
NiCr or CrSi
P1005
CODE
Z
Y
E
H
K
± 10 ppm/°C
± 25 ppm/°C
± 50 ppm/°C
± 100 ppm/°C
Notes
(1)
Reduced temperature operating range:
[0 °C; + 70 °C] option available for (- 25 °C; + 85 °C): 0027
and [- 55 °C; + 155 °C]: 0079
(2)
R > 39
Ω
on request for lower values.
P1206
POWER DERATING CURVE
Rated Power (%)
P1505
100
80
60
P2010
40
20
0
0
20
40
60 70
80
100
120
140 155
Ambient Temperature in °C
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62
Note
•
Size 2512 under development. Please consult Vishay Sfernice.
(3)
5 ppm/°C in a reduced operating range (0 °C; + 70 °C). Options
available for operating range (- 25 °C; + 85 °C) and (- 55 °C;
+ 155 °C) upon request with price adder.
Document Number: 53017
Revision: 15-Mar-10
For technical questions, contact:
sfer@vishay.com
P
High Precision Wraparound - Wide Ohmic Value Range
Vishay Sfernice
Thin Film Chip Resistors
POPULAR OPTIONS
For any option it is recommended to consult Vishay Sfernice for availability first.
Option: Enlarged terminations:
For stringent and special power dissipation requirements, the thermal resistance between the resistive layer and the solder joint
can be reduced using enlarged terminations chip resistors which are soldered on large and thick copper pads acting as heatsink
(see application note: 53048 Power Dissipation in High Precision Vishay Sfernice Chip Resistors and Arrays (P Thin Film, PRA
Arrays, CHP Thick Film)
www.vishay.com/doc?53048.
Option to order: 0063 (applies to size 1206/1505/2010).
DIMENSIONS
(Option 0063) in millimeters
Bottom view for mounting
A
Uncoatted
ceramic
Enlarged
termination
B
F
D
E
A
CASE
SIZE
MAX. TOL.
+ 0.152
MIN. TOL.
- 0.152
NOMINAL
1206
1505
2010
3.06
3.81
5.08
B
MAX. TOL.
+ 0.127
MIN. TOL.
- 0.127
NOMINAL
1.60
1.32
2.54
E
MAX. TOL.
+ 0.13
MIN. TOL.
- 0.13
NOMINAL
0.40
0.48
D
MAX. TOL.
+ 0.13
MIN. TOL.
- 0.13
NOMINAL
1.215
1.59
2.25
0.63
0.50
0.76
NOMINAL
F
MIN.
MAX.
Note
• Case size 2512 under development. Please consult Vishay Sfernice.
SUGGESTED LAND PATTERN
(Option 0063)
G
min.
X
max.
Z
max.
CHIP SIZE
1206
1505
2010
DIMENSIONS (in millimeter)
Z
max.
3.91
4.66
5.93
0.50
G
min.
X
max.
1.73
1.45
2.67
Note
• Case size 2512 under development. Please consult Vishay Sfernice.
Document Number: 53017
Revision: 15-Mar-10
For technical questions, contact:
sfer@vishay.com
www.vishay.com
63
P
Vishay Sfernice
High Precision Wraparound - Wide Ohmic Value Range
Thin Film Chip Resistors
Option: Tightest Temperature Coefficient on Extended Temperature Range
Option to order 0027:
TCR: 5 ppm/°C in [- 25 °C; + 85 °C] temperature range. Price adder will apply. Please consult Vishay Sfernice.
Option to order 0079:
TCR: 5 ppm/°C in [- 55 °C; + 155 °C] temperature range. Price adder will apply. Please consult Vishay Sfernice.
Option: High Temperature
For applications such as down hole drilling, high temperature withstanding is required. Vishay Sfernice offers an option
for utilization on extended temperature range: [- 55 °C; + 215 °C] powered (and up to 230 °C unpowered).
For guidance in designs, please refer to application note: 53047 Power Dissipation Considerations in High Precision Vishay
Sfernice Thin Film Chip Resistors and Arrays (P, PRA etc.) (High Temperature Application)
www.vishay.com/doc?53047.
Option to order 0031:
Recommended terminations: Gold (< 1 µ)
Performances:
Best temperature coefficient:
5 ppm/°C in [0 °C; + 70 °C]
10 ppm/°C [- 55 °C; + 155 °C]
15 ppm/°C [- 55 °C; + 185 °C]
25 ppm/°C [- 55 °C; + 215 °C]
Power rating: 0.1 x Pn
Best tolerance after high temperature assembly: 0.1 %
Long term stability: 0.5 % after 1000 h at 215 °C (ambient temperature) at 0.1 Pn
Stability after 4000 h unpowered
4500
4000
230 °C
Caution:
Performances obtained with following mounting conditions:
PCB: Polymide
Solder paste: PbSnAg (93.5/5/1.5)
3500
215 °C
3000
ΔR/R
ch/ppm
2500
2000
1500
1000
500
0
- 500 0
200
400
600
800
1000 1200 1400 1600 1800 2000 2200 2400 2600 2800 3000 3200 3400 3600 3800 4000
h
185 °C
200 °C
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64
For technical questions, contact:
sfer@vishay.com
Document Number: 53017
Revision: 15-Mar-10
PCB Design
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