EEWORLDEEWORLDEEWORLD

Part Number

Search
 PDF

A42MX24-2TQ100A

Description
FPGA, 295 CLBS, 2000 GATES, 48.24 MHz, PQFP100
Categorysemiconductor    Programmable logic devices   
File Size7MB,142 Pages
ManufacturerMicrosemi
Websitehttps://www.microsemi.com
Download Datasheet Parametric View All

A42MX24-2TQ100A Overview

FPGA, 295 CLBS, 2000 GATES, 48.24 MHz, PQFP100

A42MX24-2TQ100A Parametric

Parameter NameAttribute value
Number of terminals100
Minimum operating temperature-55 Cel
Maximum operating temperature125 Cel
Processing package descriptionPLASTIC, MO-108, QFP-100
each_compliYes
stateActive
Programmable logic typeFIELD PROGRAMMABLE GATE ARRAY
clock_frequency_max48.24 MHz
The maximum delay of a CLB module3.72 ns
jesd_30_codeR-PQFP-G100
jesd_609_codee0
moisture_sensitivity_level3
Number of configurable logic modules295
Number of equivalent gate circuits2000
organize295 CLBS, 2000 GATES
Packaging MaterialsPLASTIC/EPOXY
ckage_codeQFP
packaging shapeRECTANGULAR
Package SizeFLATPACK
eak_reflow_temperature__cel_225
qualification_statusCOMMERCIAL
seated_height_max3.4 mm
Rated supply voltage3.3 V
surface mountYES
CraftsmanshipCMOS
Temperature levelMILITARY
terminal coatingTIN LEAD
Terminal formGULL WING
Terminal spacing0.6500 mm
Terminal locationQUAD
ime_peak_reflow_temperature_max__s_30
length20 mm
width14 mm
dditional_featureCAN ALSO BE OPERATED AT 5.0V
AD16.0 Copy Room Formats Problems
Please ask the experts: AD16.0 multi-channel design, the V1 version of the PCB was designed using Copy Room Formats, which worked very well. However, after a while, when the circuit was debugged and t...
daiduohao PCB Design
OSEK logical ring building process
[size=2]Hello everyone! I have been learning about OSEK NM recently. I have read the OSEK NM specification v2.5.3 briefly, but I am still confused about the process of building the logical ring of OSE...
zhurutang Automotive Electronics
The world's smallest gingerbread house
Travis Casagrande, a researcher at the Electron Microscopy Center at McMaster University in Canada, recently created the world's smallest "gingerbread house", which is only 10 x 6 microns in size....
dcexpert DIY/Open Source Hardware
I have a problem with using the eclipse that comes with altera. Can anyone tell me what I have used?
[backcolor=rgb(222, 240, 251)][font=Tahoma, Helvetica, SimSun, sans-serif]I just want to debug the C language to see if there is any error, but this prompt always appears. I have read various tutorial...
yym86202 Altera SoC
The Three Realms of Oscilloscopes
...
至芯科技FPGA大牛 FPGA/CPLD
Problems with the snubber circuit
As shown below, this is the output side of the push-pull boost circuit After the transformer output is full-wave rectified by the rectifier bridge, Is the circuit of L1, D1, R1, and C1 an absorption c...
shaorc Analog electronics

Technical ResourceMore

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2024 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号